Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[LightningZ71]

There isn’t a lot of ‘translation’ layer going on in servers. If you read the interview I linked you will see that even architectural differences with the same instruction set matter. If software is optimized for AVX512 then those are the x86 CPUs that hyperscalers want.

One of the biggest issues for ARM was a ‘standardized’ plug and play server core with a stable release of Linux.

Volume matters. AMD has a 50% margin for architecture. They don’t develop process. That is the margin that hyperscalers have to license Neoverse cores, customize a processor for their specific loads and develop the software stack. AWS was already fabricating a DPU, Nitro with TSMC in the millions and Graviton was an easy extension with savings on purchase and power.

The translation layer would be for client software running on their provided VM nodes. There won't be much in the way of third party RiscV software that's available for VM clients to use natively, so they'll need a translation layer for their VM instances. In house hyperscalers that just need computer clusters for themselves will use RiscV Linux instances, and recompile any inhouse applications they intend to use on it. It hasn't made financial sense to do that so far, but with ARM trying to squeeze everyone for revenue, that point will be coming.

 

[511]

He didn't say anything abt that on his post ¯\_(ツ)_/¯

you can always ask him no one is stopping you :rofl:

 

[511]

@Geddagod

https://twitter.com/x/status/1987933120889565373

 

[Geddagod]

@Geddagod

https://twitter.com/x/status/1987933120889565373

Yes, I'm hmph bruh

 

[511]

Yes, I'm hmph bruh

even than it's funny Chadmont shrank further

 

[Doug S]

Long term, the only thing that ARM's new strategy is going to do is push hyper scalers to develop RiscV products eventually. Eventually, they will need to find cost relief somewhere...

Not sure they would go RISC-V (that ISA has issues) but I agree if ARM squeezes too hard they'll go somewhere else. They can easily port their own stuff from ARM to whatever, and customers who have ARM stuff have ported it recently so another port would be little problem for them if they got lower pricing in return.

If I was in charge at a hyperscaler like Amazon or Microsoft I'd make an announcement of some sort about a backup plan in case ARM gets too greedy. Whether that's RISC-V, MIPS, licensing the rights to use an existing ISA like POWER, or developing their own doesn't matter. Bonus points if multiple hyperscalers go in with a joint announcement. The cost would be minimal (they don't need to actually start designing a chip until they decide to bring the backup plan into action) for them, and the fear of losing their revenue would keep ARM in line.

 

[regen1]

https://twitter.com/x/status/1987915707254980980

Lion Cove in ARL-H(N3B, 3MB L2 cache) is somewhere around
~4.6 mm^2, right? Those estimates put Cougar Cove on 18A a little below that. Still until something concrete comes will treat those as rough estimates.
Darkmont cluster looking good.

 

[Geddagod]

Lion Cove in ARL-H(N3B, 3MB L2 cache) is somewhere around
~4.6 mm^2, right? Those estimates put Cougar Cove on 18A a little below that. Still until something concrete comes will treat those as rough estimates.
Darkmont cluster looking good.

Yes. That's around what I got, but I also didn't include power gates in my measurement, no idea how that dude did his.

If I was in charge at a hyperscaler like Amazon or Microsoft I'd make an announcement of some sort about a backup plan in case ARM gets too greedy.

Idk how seriously ARM is going to take though unless they actually start making progress on those chips. I'm sure ARM would hear about it if it was just an empty threat, even if it's unofficially.

 

[LightningZ71]

Instead of going with RiscV, they'll form an industry consortium and develop an "OpenRISC" ISA? I like that idea. It'll only take a few years of lawsuits and licensing to get past all the payments for the most obvious ISA components ever.

 

[OneEng2]

If Zen 6 is already out there in the wilderness, it will have to be Zen 7 in ~2028?

AMD needs to compress the cadence back to 18 months...

The cadence will always be linked to the process change cadence.... which is getting longer and giving less improvement each shrink .... so if anything, I am guessing the cadence is going to double not shrink.

Then what? Now you are at mercy of fluctuating and declining PC market.

Good point. Not a great strategy to put all your chips on one market ..... that is declining.

 

[Geddagod]

The cadence will always be linked to the process change cadence.... which is getting longer and giving less improvement each shrink .... so if anything, I am guessing the cadence is going to double not shrink.

Tocks can be on the same process, like Zen 2 to Zen 3.

 

[Doug S]

Idk how seriously ARM is going to take though unless they actually start making progress on those chips. I'm sure ARM would hear about it if it was just an empty threat, even if it's unofficially.

I'm not suggesting an empty threat. You have to do it, but you ALSO have to announce it, because you don't want to take the chance that ARM doesn't hear about it. You want to them to know it, and to know that you want them to know it. The cost of implementing such a backup plan is tiny versus the cost of ARM turning the screws on you royalty wise.

The other alternative is they could do like Apple and sign a long term deal that specifies royalty rates so ARM doesn't have any ability to raise prices on you. You'd have to agree to more than you are paying now, but if you have certainty of rates for a decade or more you've removed your business risk in that area.

 

[DavidC1]

Lion Cove in ARL-H(N3B, 3MB L2 cache) is somewhere around
~4.6 mm^2, right? Those estimates put Cougar Cove on 18A a little below that. Still until something concrete comes will treat those as rough estimates.
Darkmont cluster looking good.

So 18A is somewhat more dense than N3B.

Based on this data:
-Darkmont is 14% more dense than Skymont
-It's not a pure Tick, but something greater. It might suggest 20% logic advantage of 18A over N3B
-P core size reductions are no less than E cores. Remember, the P core includes the L2 cache, which increased in capacity by 20% over the predecessor, while the E cores stayed the same. If anything, P cores shrunk a bit more than E cores.
-Official data puts SRAM sizes at, 0.023um2 for HCC, 0.021um2 for HDD 18A, and 0.0199 for N3B HD.

So the possible implication is that Novalake uses N2 on high end because Intel is still struggling to get clocks high up while they use 18A on lower chips because it'll be much cheaper to produce.

 

[511]

So 18A is somewhat more dense than N3B.

Based on that the caches aren't scaling. Actually according to official data, N3B's HD SRAM is 16% more dense than 18A HCC, and 6% more than 18A HDD. Darkmont is 14% more dense over Skymont. This isn't pure shrinks either. The cores have uarch enhancements greater than typical Ticks. The P core size reductions do not seem lower than E cores. If anything, P cores have benefitted more. That does jive with Intel 18A presentation that HCC SRAM has shrunk more than HDD over Intel 3. Remember the P core number includes the 1.2x increased L2 cache size, while the E core cluster has same capacity.

So the possible implication is that Novalake uses N2 on high end because Intel is still struggling to get clocks high up while they use 18A on lower chips because it'll be much cheaper to produce.

i want to see high res image and compare without the L2 blocks for both Darkmont and cougar but it's >3X the area difference for Core+L1 the peak performance is not known for both cores on 18A

 

[DavidC1]

i want to see high res image and compare without the L2 blocks for both Darkmont and cougar but it's >3X the area difference for Core+L1 the peak performance is not known for both cores on 18A

If we apply 14% density for logic, then the P core size is only possible if it's also using HDD cells for SRAM. Using HCC cells would make it quite a bit greater in size versus Lion Cove. I got 4.498mm2 using the official SRAM number and 14% logic scaling. This would partially explain the lower clocks.

TPU article said this: https://www.techpowerup.com/review/intel-panther-lake-technical-deep-dive/5.html

The Cougar Cove performance core succeeds Lion Cove and brings a series of targeted refinements focused on efficiency rather than higher peak clocks.

The P cores are doing relatively better. The gains should end up greater than Darkmont. This is no excuse. This is likely executing on things they couldn't on Lion Cove(because it underperformed the typical 20% gain).

 

[dullard]

you can always ask him no one is stopping you :rofl:

He did finally share the image (with a credit to Chips and Cheese 9):

https://pbs.twimg.com/media/G5crYNqbcAAAsCH?format=jpg&name=large

Previous die shot for comparison: https://pbs.twimg.com/media/G202aoKXMAA4TGl?format=jpg&name=4096x4096

 

[Fjodor2001]

So the possible implication is that Novalake uses N2 on high end because Intel is still struggling to get clocks high up while they use 18A on lower chips because it'll be much cheaper to produce.

Which NVL-S SKUs would be considered "lower chips" in that case?

Also, any chance they could initially launch NVL-S using N2 for (some of?) the compute tiles and then do a refresh later where they switch to 18A, when the latter one clocks high enough?

 

[Geddagod]

He did finally share the image (with a credit to Chips and Cheese 9):

https://pbs.twimg.com/media/G5crYNqbcAAAsCH?format=jpg&name=large

View attachment 133765

Previous die shot for comparison: https://pbs.twimg.com/media/G202aoKXMAA4TGl?format=jpg&name=4096x4096

Much too low rez, but just as important, hard to tell where the die ends/where the scribe lines should be.

Which NVL-S SKUs would be considered "lower chips" in that case?

4+0 T-T
Previously thought the 4+8 dies would also be on 18A

Also, any chance they could initially launch NVL-S using N2 for (some of?) the compute tiles and then do a refresh later where they switch to 18A, when the latter one clocks high enough?

Don't see why this can't be the case for RZL.
Also heavily dependent on how much IFS is going to push for high performance/high voltage performance instead of focusing on other aspects of the node.

 

[511]

4+0 T-T
Previously thought the 4+8 dies would also be on 18A

4+0+4 is the volume config and should be cheap like it only contains 4P Cores and 2P cores sharing 4MB L2 with 2 Ring Stops

Don't see why this can't be the case for RZL.
Also heavily dependent on how much IFS is going to push for high performance/high voltage performance instead of focusing on other aspects of the node.

RZL is big unknown

 

[DavidC1]

Also heavily dependent on how much IFS is going to push for high performance/high voltage performance instead of focusing on other aspects of the node.

??

We're talking Intel here. Them failing to meet project goals doesn't mean they haven't aimed for high performance.

 

[511]

https://twitter.com/x/status/1988881875243340113

So APX/AVX 10.2 Confirmed for NVL

 

[511]

??

We're talking Intel here. Them failing to meet project goals doesn't mean they haven't aimed for high performance.

they should tone down their Higher performance focus and shift to Perf/watt and Density as well

 

[RTX]

How accurate are those dimensions?

 

[RTX]

Yes, I'm hmph bruh

https://twitter.com/x/status/1988680552837468569

Does LNL use 2-1 anywhere?

 

[Geddagod]

https://twitter.com/x/status/1988680552837468569

Does LNL use 2-1 anywhere?View attachment 133835

that dude (not professional principia, the other one) is actually idiotic lol.
But also, yea, LNL uses 2-1 for the iGPU

How accurate are those dimensions?

The resolution and not knowing where the scribe lines are make it extremely bad in finding out the area.