Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[OneEng2]

It's 400Mhz lower clock 4.7 vs 5.1 has like 6% IPC Improvements so the best case is PTL will have same st as arl but lower power

In laptop and in DC applications, I believe the max performance will be strictly limited by power. In this regard, efficiency improvements should lead to better performance at the same power.

 

[dullard]

In laptop and in DC applications, I believe the max performance will be strictly limited by power. In this regard, efficiency improvements should lead to better performance at the same power.

While what you posted is correct, I just fail to see the compelling argument to buy a low-power ultra-light laptop for distributed computing. Will someone do it? Yes. But, that is basically an edge case.

 

[LightningZ71]

Overall, lithography tends to push nT performance per sq/mm of core silicon as well as nT performance per watt of power over anything else. Denser XTORS let you make more complicated core designs, which certainly helps 1T performance, but nT performance always seems to increase by a greater degree. As we hit the limits of transporting heat away from those XTORS, nT performance scaling is going to suffer for a bit as clocks have to slow down.

 

[DavidC1]

It depends on how it's designed, no? Why would parameterizing most of the design to work with an arbitrary number of decode clusters should be difficult? I'd guess that only a few blocks would require separate logic for each configuration. Would that really qualify as a different architecture? I know it would with old school design methodology, but with current design and synthesis flows it could be almost entirely reuse.

Remember we're looking at the mile-high level. There are countless engineering decisions that goes into making a core.

The simplest way of doing what you suggest is just adding more decode clusters. However, the gains of doing that will be small, in the region of few single digit %. Extra decode *must* come with expanding and innovation everywhere else. The few % gain of just adding decoders can be done in a much more power, area, and time efficient way, which is addressing bottlenecks in a targetted way. That in Intel term is called a Tick. Look at how small the scale of changes on Crestmont is.

So why do they add more decoders if it's so small of a gain? Because a trillion different teeny rocks end up being a beach. It's just part of a big picture. Thus a theoretical 5x3 would be a massive change over a 4x3.

Also, at the high end simplicity has always translated into making more complex in a more efficient way. So when they tell you it's 30% faster with a new design methodology, at the high end it'll be used for putting more performance in.

 

[dullard]

Panther Lake launch event: Jan 5, 2026 3 PM PST

Intel at CES

Join us in Las Vegas, January 5-9, 2026, for CES and experience the global launch of the latest Intel® Core™ Ultra Series 3 Processors

www.intel.com

 

[dullard]

It is though the memory speed is LPDDR5X 9600 max supported and it won't be enough to feed 12Xe3 and Xe3 is a major architecture change expect as big improvement as Xe2 was over Xe1.

At least one company is launching Panther Lake with capability of up to LPDDR5x-10667: https://videocardz.com/newz/gmktec-...0-panther-lake-12xe-with-128gb-lpddr5x-memory

 

[511]

At least one company is launching Panther Lake with capability of up to LPDDR5x-10667: https://videocardz.com/newz/gmktec-...0-panther-lake-12xe-with-128gb-lpddr5x-memory

Yeah just saw this is good for the GPU I guess extra 5-10% FPS improvement in memory bound scenarios

 

[poke01]

Panther Lake launch event: Jan 5, 2026 3 PM PST

Intel at CES

Join us in Las Vegas, January 5-9, 2026, for CES and experience the global launch of the latest Intel® Core™ Ultra Series 3 Processors

www.intel.com

I guess late jan or early feb to buy for countries other than USA and china.

 

[511]

Yeah looks like it

 

[regen1]

CQDIMM

JEDEC Renames 4-Rank DDR5 CUDIMMs to CQDIMM for Standardization

JEDEC has introduced a new naming rule for emerging high-capacity DDR5 memory modules. As 4-rank unbuffered DIMMs begin entering production, the organization is replacing the former CUDIMM label with a new, dedicated term: CQDIMM.

www.guru3d.com

Already announced on some Z890 platform

ADATA and MSI Launch the World's First 4-RANK DDR5 CUDIMM Memory Module

ADATA Technology, a global leader in memory and storage solutions, today announced the launch of the world's first ADATA High Capacity DDR5 4-Rank CUDIMM Memory Module, jointly developed with leading motherboard manufacturer MSI. This groundbreaking module features the innovative 4-RANK...

www.techpowerup.com

 

[dullard]

Panther Lake is currently in production in Oregon. But, the Arizona fab should ramp up in Q1 2026 with better yields and lower costs:

"Initially on any new process, we take wafers from Oregon," said John Pitzer... "Oregon is where we do all of our technology development and then move into quasi high-volume manufacturing."

"Those wafers tend to be pretty expensive. Most, if not all, of the Panther Lake wafers this year are coming from Oregon. As we transition into Q1, you will start to see wafers coming in from Arizona [which] has a much better and different cost structure, and that ramps throughout the year," Pitzer said.

https://www.tomshardware.com/pc-com...eals-and-cutting-edge-18a-process-is-on-track

 

[511]

https://twitter.com/x/status/1992086532254285869

PTL ES @3.2 Ghz

 

[poke01]

https://videocardz.com/newz/intel-arc-b390-panther-lake-igpu-shows-promising-results-in-alleged-3dmark-tests

Really good. ~7000 in Time spy

 

[poke01]

6000 in steel nomad light

 

[511]

The iGPU Score is better than M5 but package power is unknown

 

[Khato]

Probably results from a 45W configuration where it's nowhere near as efficient. Should be closer to 5k in Time Spy at 25W. Still nice to see the potential is there to scale up a fair amount when provided with more power.

 

[511]

Probably results from a 45W configuration where it's nowhere near as efficient. Should be closer to 5k in Time Spy at 25W. Still nice to see the potential is there to scale up a fair amount when provided with more power.

i don't think it's 45W it's likely t be 40W imo

 

[Magio]

Still nice to see the potential is there to scale up a fair amount when provided with more power.

From Intel's slides when they (sort of) unveiled PTL, that's the big difference vs ARL/LNL, the GPU is not a million times more performant than those at low power but it scales far higher.

For my own preferences I do hope it does well enough at the sub 30W range that manufacturers ship decent thin and lights at that TDP, but the upside on slightly chunkier designs that can handle 40+W is good news too.

 

[DavidC1]

The iGPU Score is better than M5 but package power is unknown
View attachment 134352

Some of these benchmarks favor the mobile variants too much with FP16 vs FP32. The Aztec benchmark for example needs to add 30% for Intel/AMD GPUs versus ARM because of this. The only proper synthetic benchmark is Time Spy. It's not necessarily representative of gaming performance for iGPUs because it's too demanding, but can be if you play games that run at 20-30 fps.

 

[poke01]

Some of these benchmarks favor the mobile variants too much with FP16 vs FP32. The Aztec benchmark for example needs to add 30% for Intel/AMD GPUs versus ARM because of this. The only proper synthetic benchmark is Time Spy. It's not necessarily representative of gaming performance for iGPUs because it's too demanding, but can be if you play games that run at 20-30 fps.

depends on the mobile GPU. Apple GPUs do poorly on GFXbench. It’s ARMs own Mali GPUs that do well.

In any case Steel nomad light isn’t a replacement for Time spy, it’s Steel Nomad which is much more demanding.

 

[DavidC1]

depends on the mobile GPU. Apple GPUs do poorly on GFXbench. It’s ARMs own Mali GPUs that do well.

In any case Steel nomad light isn’t a replacement for Time spy, it’s Steel Nomad which is much more demanding.

I'm talking about x86 vs ARM comparisons. The mobile benchmarks run on FP16, and the PC GPUs run on FP32, even though Intel has been capable of FP16 since Bay Trail. That's a big part of why Apple GPUs underperform in games compared to Nvidia GPUs.

 

[Josh128]

There's more than enough N2p for everyone, plus HPC GPGPU sticks are HBM/packaging limited anyway.

Well this obviously incorrect statement has aged like warm milk and has now been proven to be false by TSMC's own CEO. TSMC was not able to forecast current demand in projections from 3+ years ago, and therefore did not size their bleeding edge fabs capacity anywhere close to meeting current demand, lol.

https://www.ctee.com.tw/news/20251124700058-430501

In their speeches, Wei Zhejia and Liu Deyin both reviewed the nearly 30 years of working together and emphasized that this honor belongs to the entire TSMC team. U.S. Secretary of Commerce Howard Lutnick also paid tribute through a pre-recorded video, bluntly stating that "your leadership at TSMC has changed the world" and promoted advanced manufacturing and global technological progress, and his speech received warm applause from the audience.

When talking about the demand for AI-driven advanced processes, Wei Zhejia's tone changed, pointing out that customer demand far exceeded expectations. He revealed that according to the product planning and growth expectations of major customers, "TSMC's existing production capacity is still about 3 times short", and the advanced process production capacity is "not enough, not enough, or still not enough". He even laughed and said that he originally wanted to wear a T-shirt with the words "No more wafer" on stage, implying that the demand for wafers was too strong to digest, which became one of the most high-profile conversations of the night.

 

[LightningZ71]

No one was predicting the accounting tricks and level of imaginary money that would magically appear into existence to fund the unprecedented level of demand that they are seeing. There just wasn't enough money in existence to justify the level of build out needed for current demand. There still probably isn't.

 

[Josh128]

No one was predicting the accounting tricks and level of imaginary money that would magically appear into existence to fund the unprecedented level of demand that they are seeing. There just wasn't enough money in existence to justify the level of build out needed for current demand. There still probably isn't.

Which is exactly what I was telling him, and why AMD will prioritize wafers for AI and DC rather than DT. The insane demand materialized only in the last 2 years or so, not enough time to expand construction of fabs to meet it, therefore they cant produce enough to meet the demand.

If the demand is there , AMD'd have to be foolish not to prioritize allocation to AI and DC.

 

[LightningZ71]

With demand at such ridiculous levels, the pricing of wafers as going to go through the roof. They likely can't make a profit case for client directed wafers at this point. We're going to see trailing node products for a long time because they are far less attractive to AI/DC.