Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing Raptor Lake-U. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q1 2026.

		Intel Raptor Lake U	Intel Wildcat Lake 15W?	Intel Lunar Lake		Intel Panther Lake 4+0+4
Launch Date		Q1-2024	Q2-2026	Q3-2024		Q1-2026
Model		Intel 150U	Intel Core 7	Core Ultra 7 268V		Core Ultra 7 365
Dies		2	2	2		3
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		Intel 18-A + Intel 3 + TSMC N6
CPU		2 P-core + 8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		4 P-core + 4 LP E-cores
Threads		12	6	8		8
Max Clock		5.4 GHz	?	5 GHz		4.8 GHz
L3 Cache		12 MB		12 MB		12 MB
TDP		15 - 55 W	15 W ?	17 - 37 W		25 - 55 W
Memory		128-bit LPDDR5-5200	64-bit LPDDR5	128-bit LPDDR5x-8533		128-bit LPDDR5x-7467
Size		96 GB		32 GB		128 GB
Bandwidth				136 GB/s
GPU		Intel Graphics	Intel Graphics	Arc 140V		Intel Graphics
RT		No	No	YES		YES
EU / Xe		96 EU	2 Xe	8 Xe		4 Xe
Max Clock		1.3 GHz	?	2 GHz		2.5 GHz
NPU		GNA 3.0	18 TOPS	48 TOPS		49 TOPS

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[511]

https://twitter.com/x/status/1986817917590159753

another day another Intel Linux Engineer Improves AMD Performance

AMD should give bonus to these engineers they desrve it

 

[gdansk]

if they get laid off they know where to apply.

 

[511]

I think the layoffs are nearly over at Intel they have removed Altera and Mobileeye Employee from Intel employee count

 

[Joe NYC]

H2 26 launch similar timeframe as GNR

That's cool that Intel got all these instruction extensions into 2026 product.

Highly unlikely that they are in Zen 6. Although APX could be just a microcode update...

 

[adroc_thurston]

Although APX could be just a microcode update...

Lmaoooooo wtf are you on

 

[Joe NYC]

Isn't it just microcode change to the decoder? The modern CPUs already have far more hardware registers than number of named registers.

 

[adroc_thurston]

Isn't it just microcode change to the decoder?

No you need a completely new front-end to comprehend the new opcode space.

 

[Joe NYC]

No you need a completely new front-end to comprehend the new opcode space.

But there are no new opcodes (are there?)

It's just that the register number can go to 32 instead of 16. Most of this has likely been generalized in the original AMD64 instruction set.

 

[adroc_thurston]

But there are no new opcodes (are there?)

They have a whole new REX2 prefix for it.
Please read the spec.

 

[511]

APX is not coming any time soon on Zen

 

[OneEng2]

Getting the best ST possible + getting the most MT in the least area possible.

Fair point. Just curious if it actually achieves this where it matters.

In desktop there aren't like more than a paltry % of people that care about high core counts. Very few applications can use it.

I am wondering if a "mont" based core can compete in a DC environment in PPA with Zen 6?

It works. It really does but only in desktop.

It's a theory! I tend to agree. We will finally be able to see for sure next year.

Im more interested to see how the 256C Venice D compares to the 288c CWF, in both performance and power efficiency. 288 is exactly 12.5% more than 256, so core for core comparisons will be pretty straightforward between the two. I suspect it will be a bludgeoning in favor of Zen 6D.

Agree. High core DC applications are likely aways power limited. It will be very interesting to see how this works out.

I assume “ringbus issue” is not synonymous with ringbus frequency?

You are correct. I am throwing the whole "Latency" issue on that one term. Still, the latency is sooooo bad, one has to wonder if they improved that one aspect in NVL ..... what kinds of gains could be had?

This is what I mean AVX-512 should have been AVX3-256. Even in servers the 512-bit gets you only ~15% in average. It's the ISA that's bringing you most of the gains over AVX2. You hurt everything else just to satisfy the HPC crowd. In CPUs you are bound by everything else - you could have more L/S units, more memory bandwidth, more cache bandwidth, which speeds up every other application. I've seen some tests for a Xeon where it said it got ~10% of theoretical performance based on Flops. Heck, if you use Intel Linpack and test for Flops it doesn't even get 100% of the theoretical Flops on a test that is designed to test Flops!

You may be right about the move from AVX-256 to AVX-512. Double the transistors for 15% improvement. Going from NO AVX to AVX512 was huge though.

The problem I see for Intel is that coming from behind, they may well need that 15%.

N2 isn't really a 2 node jump, more like 1 at best.

Agree. This is the new reality. MLID for sure. I think the current state of affairs is that transistor density doubles about every 10 years!

After aiming for greater ST performance at expense of SMT (with very mixed results), the new orders from the new leadership are to bring SMT back.

It was foolish IMO for them to drop it.

SMT vs no SMT can't be compared on ISO basis. I assume the LNC presentation about SMT having significant power and die area disadvantage has to do with big picture, because on the surface it's about adding few extra registers, which is insignificant die area increase.

AMD claims SMT adds ~5% to the transistor budget. In DC they get around 1.4x performance from it. I can't think of anything else that 5% would be better used for. Additionally, benchmarks show only a trivial increase in power use under SMT.

 

[regen1]

10nm also threw a wrench in Intel's design Schedule GLC was supposed to come out in 2016-17 !! they simply killed themselves

10nm is an epic disaster but GLC(if you mean Golden Cove) was never possible in 2016-17. Come on!

 

[adroc_thurston]

APX is not coming any time soon on Zen

?

10nm is an epic disaster but GLC(if you mean Golden Cove) was never possible in 2016-17. Come on!

If we go with the OG ticktock timeline we'd get Broadwell H1'14, Skylake H1'15, Cannon Lake H1'16 and the next tock (would-be GLC) H1'17.

Obviously, 14nm slipped so most of CNL would've been 2017 thus shifting the tock to '18 but yeah.

 

[poke01]

I’m sure if a big customer wanted a low power high ST core, AMD/Intel would make one.

To me what’s most impressive is the fact that Apples CPU core is not that far from Panther Lake clock. We are approaching that area where very wide CPU cores are approachingx x86 mobile clocks.

I hope Nova Lake mobile has increased clocks, especially the H lineup to like 5.8GHz.

 

[adroc_thurston]

I’m sure if a big customer wanted a low power high ST core, AMD/Intel would make one.

It ain't *that* easy.

I hope Nova Lake mobile has increased clocks, especially the H lineup to like 5.8GHz

You'll be lucky to have 5.8 on DT.

 

[Joe NYC]

You'll be lucky to have 5.8 on DT.

On N2P? That would be bad...

 

[adroc_thurston]

On N2P? That would be bad...

5.7 on N3 is also bad.

 

[regen1]

?

If we go with the OG ticktock timeline we'd get Broadwell H1'14, Skylake H1'15, Cannon Lake H1'16 and the next tock (would-be GLC) H1'17.

Obviously, 14nm slipped so most of CNL would've been 2017 thus shifting the tock to '18 but yeah.

Err you forgot ICL(Sunny Cove), the jump from Cannon Lake was Ice Lake.
Golden Cove, even if node issues are ignored, could never have been out in 2017 even. 2019+ at the very least. The work on it was nowhere concluded by that period(2016-17).

 

[adroc_thurston]

Err you forgot ICL(Sunny Cove), the jump from Cannon Lake was Ice Lake.
Golden Cove, even if node issues are ignored, could never have been out in 2017 even. 2019+ at the very least. The work on it was nowhere concluded by that period(2016-17).

Oh wait yeah sorry, I forgot SNC was a thing.
Yeah that would make GLC 2019 with the OG schedule.

 

[Doug S]

@Joe NYC Skill issue. Can't be explained any other way. Also human factors like lack of motivation/hope for future. Lot of the world sees x86 land as no future. Imagine being that engineer. A self fulfilling prophecy where x86 dies not because it can't actually be close enough but people believe it can't be overcome.

I think a good part of it is what is seen as "sexy" and exciting, versus staid and boring. If you're a quality CPU designer who can get a job anywhere and its 2015, do you want to work at boring corporate Intel with layers of middle management and people on your team that have been the same place their entire career, dysfunctional AMD that could go bankrupt any moment, or at Apple where they are doing new exciting stuff that pushes the limits of silicon design in power restricted form factors?

In 2025 working on Apple's CPUs is no longer where its at of course, now it is AI, AI and then AI. Nvidia is the king, other megacaps trying to compete with the king, and various startups forging their own path like Cerebras. With the bonus that if you pick the right startup and it gets acquired or IPOs before the AI bubble bursts you have a chance of becoming wildly rich.

 

[Doug S]

APX is not coming any time soon on Zen

Even when it arrives it is not going to make a whole lot of difference for a while. Other ISA changes like the addition of AVX-512 operate in a very limited portion of your code. The few sections where the code would really benefit from it can check if AVX_512 is supported and follow an AVX_512 codepath. Libraries can do the same, and then programs can benefit from AVX_512 even if they aren't recompiled. That makes it pretty easy to support, and as a dev you pretty much know whether your software will benefit from AVX_512 and thus whether it is worth your time.

That's not the case with APX. The benefits are spread thinly across pretty much everything, so it isn't practical for code to check if APX is supported and follow a different path. The only way to support it is to build a new binary, which won't be worth it except for some niche apps that need every last bit of performance (and benchmarks of course, they will be the FIRST thing ported lol) So the rollout will be something like the rollout of 64 bit binaries - and those got a bigger boost going to 16 registers (though there was also a hit from the effectively smaller cache when pointers doubled in size that affected pointer heavy code to a larger extent) than APX will give you going to 32.

 

[Joe NYC]

Even when it arrives it is not going to make a whole lot of difference for a while. Other ISA changes like the addition of AVX-512 operate in a very limited portion of your code. The few sections where the code would really benefit from it can check if AVX_512 is supported and follow an AVX_512 codepath. Libraries can do the same, and then programs can benefit from AVX_512 even if they aren't recompiled. That makes it pretty easy to support, and as a dev you pretty much know whether your software will benefit from AVX_512 and thus whether it is worth your time.

That's not the case with APX. The benefits are spread thinly across pretty much everything, so it isn't practical for code to check if APX is supported and follow a different path. The only way to support it is to build a new binary, which won't be worth it except for some niche apps that need every last bit of performance (and benchmarks of course, they will be the FIRST thing ported lol) So the rollout will be something like the rollout of 64 bit binaries - and those got a bigger boost going to 16 registers (though there was also a hit from the effectively smaller cache when pointers doubled in size that affected pointer heavy code to a larger extent) than APX will give you going to 32.

I also have a feeling that this will be a whole new executable, almost like 64 bit vs. 32 bit. Unlikely it will not be treated like a code path within existing executable.

If 4 extensions are available, starting from certain generation of CPUs, on both Intel and AMD sides, they may just treat it as x86-64 V2.

 

[Joe NYC]

APX is not coming any time soon on Zen

If Zen 6 is already out there in the wilderness, it will have to be Zen 7 in ~2028?

AMD needs to compress the cadence back to 18 months...

 

[Thunder 57]

10nm is an epic disaster but GLC(if you mean Golden Cove) was never possible in 2016-17. Come on!

Yea I saw that and was thinking maybe Cannon Lake, certainly not GLC. That's just a mistake or revisionist history of "what could have been".

 

[DavidC1]

Maybe Intel's plan was to have a line of E-Core servers for highly MT tasks and than SMT less P-Cores for high ST tasks, except the P-Core did not exactly deliver much in terms of ST. Maybe the goal was faster iteration with SMT-less P-Cores, but now, it seems that market forces are punishing Intel for removing SMT from P-Cores and are not embracing E-Core servers nearly to the extend Intel anticipated.

We can't even conclude this, because they just started. They don't even have the second variant of the E core servers yet. And it plays a greater role than money and marketshare, which is keeping ARM out of the server market. Because there's always a tipping point, where if it gains enough share, it'll all be ARM. The share might be 5%, but the thing on the line is the future of not just Intel, but x86. So that 5% is worth it even if it's losing money. Same thing with Lunarlake. And Silvermont. Silvermont Tablets were critical in that it stopped Win 8 ARM tablets taking more share, because it was competitive in performance without needing the ARM tablet to be in binary translation mode. If you can't beat something natively, what hope do you have when it needs to be translated? Lunarlake is stopping Qualcomm advances right now.

Now, it is possible that this short-term thinking is indeed what the finance company named Intel thinks.

I could see this being a factor at Intel, especially their P-Core team, but not at AMD. AMD team is flying high, lots of adrenaline, conquering server and desktop segments. With notebook leadership within eye sight.

AMD has a same problem long term. They need to compete with Lunarlake level battery life very soon. Because right now they don't feel the need to since they can double revenue just by killing Intel. Then what? Now you are at mercy of fluctuating and declining PC market. If they are so competent, why are they just repeating/copying Intel of 2007-2014? What were the public perception of Intel during those years? Exactly like AMD now. At least Intel proved with Silvermont and Lunarlake that you can get ARM levels of power efficiency. AMD hasn't.

I think this will be worth revisiting when real first class effort - Intel Clearwater Forest and AMD Zen 6 Dense are on the market.

Because, for the first time, both Intel and AMD are aiming to compete head on with Arm in the server market. I think it is premature write them off.

I'm not writing them off, but every year it gets more dire in the big picture. Oh no, deaths won't happen suddenly. It's like what they say with investments. Nothing goes up or down in a straight line.

Threshold voltages are well below 0.6V now.

You can't clock nothing useful at those voltages. If you sold a product based on that, the product will be laughed off the market. It would have worse enthusiast perception than the original Atom. Because those fundamentals apply. That's why they jack 1.3V into the desktop chips. Even if you could lower voltage by 30%, what happens after that? The scaling were gained significantly by reducing voltages in the 90's.

I’m sure if a big customer wanted a low power high ST core, AMD/Intel would make one.

Lack of a "want" isn't why Intel failed. They just couldn't. Apple transitioned away from Intel, because they lacked the capability of making cores they wanted.