Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing Raptor Lake-U. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q1 2026.

		Intel Raptor Lake U	Intel Wildcat Lake 15W?	Intel Lunar Lake		Intel Panther Lake 4+0+4
Launch Date		Q1-2024	Q2-2026	Q3-2024		Q1-2026
Model		Intel 150U	Intel Core 7	Core Ultra 7 268V		Core Ultra 7 365
Dies		2	2	2		3
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		Intel 18-A + Intel 3 + TSMC N6
CPU		2 P-core + 8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		4 P-core + 4 LP E-cores
Threads		12	6	8		8
Max Clock		5.4 GHz	?	5 GHz		4.8 GHz
L3 Cache		12 MB		12 MB		12 MB
TDP		15 - 55 W	15 W ?	17 - 37 W		25 - 55 W
Memory		128-bit LPDDR5-5200	64-bit LPDDR5	128-bit LPDDR5x-8533		128-bit LPDDR5x-7467
Size		96 GB		32 GB		128 GB
Bandwidth				136 GB/s
GPU		Intel Graphics	Intel Graphics	Arc 140V		Intel Graphics
RT		No	No	YES		YES
EU / Xe		96 EU	2 Xe	8 Xe		4 Xe
Max Clock		1.3 GHz	?	2 GHz		2.5 GHz
NPU		GNA 3.0	18 TOPS	48 TOPS		49 TOPS

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[511]

if you compare node jumps of past to present than yeah N4 to N2 is like smaller than a full node jump in density and that is comparing the densest library of N4 which is 143mxto/mm2 and 236mxtor/mm2 to be a 1.65X Density Increase in past we had like 2.0X

 

[DavidC1]

if you compare node jumps of past to present than yeah N4 to N2 is like smaller than a full node jump

Pentium 4 went from 2GHz to 3.2GHz with same power limit and half the die size. The first real brake was with FinFET and Ivy Bridge. Second is GAA.

Of course, there was no doubt circuitry innovation needed to get those gains too, but that also hit the brakes years ago. When Crusoe introduced new circuit innovations, they got less from new process because the new circuit was essentially addressing weaknesses from current process which would be brought with new process anyways.

We had 5V CPUs, but now they are close to the ~0.6V threshold voltage. Easy voltage scaling died with 0.13u, but you still got enormous gains from gate length and capacitance reductions, which died with FinFET. The hobby and power circuitry land is still 5V, 3.3V, and 1.8V, reflecting the history of computing.

 

[Joe NYC]

The trick is not doing the Intel P core way, which causes bloat. You need innovation otherwise which doesn't fall from the sky but new ideas from engineers. This is what @OneEng2 overlooks. The E core had new innovation to get that "catchup". Predecode bits in L1, multi-level predecode cache, Clustered decode, nanocode, they are all new ideas. Further efficient gains will need additional new ideas.

That's what I meant by constraints. You can bloat the core, with returns diminishing fast.

But if you limit yourself to only to those ideas / features / sizes of elements that translate to most direct impact on performance, that acts as a constraint.

With that said, Zen 6 is overdue for ST uplift, after Zen 5's biggest gains came from (S)MT and full AVX-512 implementation.

We will see about what direction Intel P-Cores take. After aiming for greater ST performance at expense of SMT (with very mixed results), the new orders from the new leadership are to bring SMT back. Likely still on the P-Cores, before the Unified cores... That's probably a big monkey wrench for the P-Core team...

 

[DavidC1]

We will see about what direction Intel P-Cores take. After aiming for greater ST performance at expense of SMT (with very mixed results), the new orders from the new leadership are to bring SMT back. Likely still on the P-Cores, before the Unified cores... That's probably a big monkey wrench for the P-Core team...

One could argue if Cougar Cove just after 1 year offers sizable gains(5-10%), it's basically a fixed Lion Cove. Because LNC gains looked dismal considering the scale of changes, and while Cougar Cove changes seem nice, the 5-10% gain is surprisingly high relatively speaking.

That's what I meant by constraints. You can bloat the core, with returns diminishing fast.

I don't think they'll reach such limit until they reach Apple levels of efficiency, or at least ARM vendor levels.

 

[511]

One could argue if Cougar Cove just after 1 year offers sizable gains(5-10%), it's basically a fixed Lion Cove. Because LNC gains looked dismal considering the scale of changes.

I don't think they'll reach such limit until they reach Apple levels of efficiency, or at least ARM vendor levels.

Cougar is smaller as compared to Lion Cove so there is that as well

 

[DavidC1]

Cougar is smaller as compared to Lion Cove so there is that as well

I speculate there's some influence by E core team already.

We will see about what direction Intel P-Cores take. After aiming for greater ST performance at expense of SMT (with very mixed results), the new orders from the new leadership are to bring SMT back. Likely still on the P-Cores, before the Unified cores... That's probably a big monkey wrench for the P-Core team...

And I hope this isn't just for saving face sake, because high level management tends to do this. There's an unavoidable negative part about SMT, which is increased difficulty of validation. The only two vendors having execution issues reinforce my belief that over long time, it's a loss. This negates any other advantage from negligible die size gains and big MT improvements.

 

[511]

I speculate there's some influence by E core team already.

Stephen Robinson is the lead x86 architect and has been for quite some time

And I hope this isn't just for saving face sake, because high level management tends to do this. There's an unavoidable negative part about SMT, which is increased difficulty of validation. The only two vendors having execution issues reinforce my belief that over long time, it's a loss.

SMT has certain benefits like VMs

 

[Joe NYC]

I don't think they'll reach such limit until they reach Apple levels of efficiency, or at least ARM vendor levels.

It remains a mystery why the x86 vendors still have not, without simultaneously losing ability to achieve high clock speeds.

Just my opinion: both Intel and AMD have bigger core design teams and higher budgets than Apple. And even if not higher than Apple, definitely higher than Nuvia.

And, it's not like both Intel and AMD did not have time to catch up. M1 was released at around the same time as Zen 3, just a year ahead of ARL.

Whatever "inspiration" M1 had, it should have made its way to Zen 5 / LNC...

 

[511]

Well Zen4/5 would already have been in design phase when M1 Came out it takes a lot of time to do stuff remember ARL Definition was sometime in 2019-20 before M1 we would know by Zen6/NVL what did Intel/AMD does with their Arch

 

[DavidC1]

@Joe NYC Skill issue. Can't be explained any other way. Also human factors like lack of motivation/hope for future. Lot of the world sees x86 land as no future. Imagine being that engineer. A self fulfilling prophecy where x86 dies not because it can't actually be close enough but people believe it can't be overcome.

SMT has certain benefits like VMs

Server needs to have a significant modified core then. Because it's a loss everywhere. If it takes 13 months instead of 12, then over 10 years, it's a near full year loss. Glenn Hinton, the architect of Nehalem is quoted as saying "we could have got more performance, but for the sake or mitigating risk, we chose not to". David Kanter of RWT on his Nehalem article said validation is "extremely difficult". So there's always a risk of messing things up seriously, even if you ignore the recent security pitfalls. Or, it takes more time to do it properly. The thing is, you have to do it with every new modification.

SMT vs no SMT can't be compared on ISO basis. I assume the LNC presentation about SMT having significant power and die area disadvantage has to do with big picture, because on the surface it's about adding few extra registers, which is insignificant die area increase.

What about SMT - which requires increased risk and validation times versus no-SMT which does not? How much better is SMT then?

 

[511]

But Intel/AMD has to sell the processor if the clients Demand SMT what are you gonna do? say no? the only reason LBT decided to bring SMT back is cause the demand from customer. AMD/Intel need sell to other people so they have to listen to their customers as well they don't have Apple level control

 

[DavidC1]

But Intel/AMD has to sell the processor if the clients Demand SMT what are you gonna do? say no? the only reason LBT decided to bring SMT back is cause the demand from customer. AMD/Intel need sell to other people so they have to listen to their customers as well they don't have Apple level control

Cause their CPUs suck now. If they found an alternative then there would be no complaint. Same as Netburst MHz vs Core 2.

 

[511]

Well no one has another option also AMD/intel handily beat Apple if you use AVX-512 cause no one beside them make CPU also Apple is just giving the core more resources if you compare the resourcing between Intel/AMD vs Apple you will realize the difference.
Even M1 has more resources than Z5/LNC in many regards

 

[DavidC1]

Well no one has another option also AMD/intel handily beat Apple if you use AVX-512 cause no one beside them make CPU also Apple is just giving the core more resources if you compare the resourcing between Intel/AMD vs Apple you will realize the difference.
Even M1 has more resources than Z5/LNC in many regards

511, the M5 can go in a PHONE!

Enterprise/Datacenter only companies will die. This is a long term loss. Efficiency comes from constraints(which is a human thing), two of which datacenter loses: Cost and size. This is the history of computing. We're seeing it right now even with AMD and Intel. Phones and Tablets have even bigger of a constraint. RISC vs Intel lost because Intel is used to optimizing for much cheaper, smaller, and much lower power. What the consumer oriented companies do is then they bring that same optimization to datacenter, and kills all datacenter-only companies. Nvidia killed all datacenter graphics companies. The Intel E core team had constraints and under pressure to execute, or be eliminated. The star team P core didn't.

With M4 people said it only beats it in Geekbench because of SME optimization. Now M5 beats it in Cinebench. What's the excuse now? With M3 it beat all laptop processors. Slow, but rather steady.

 

[Joe NYC]

Well Zen4/5 would already have been in design phase when M1 Came out it takes a lot of time to do stuff remember ARL Definition was sometime in 2019-20 before M1 we would know by Zen6/NVL what did Intel/AMD does with their Arch

If Tick / Tock still applies, then on AMD side, Zen 5 was a Tock (bigger changes) and Zen 6 will be a Tick. So, so I wonder what parts of M1 approach can make it to Zen 6. So, wait until Zen 7?

I am guessing that Intel LNC was a Tock, so Intel is still some ways to another Tock...

 

[Joe NYC]

And I hope this isn't just for saving face sake, because high level management tends to do this. There's an unavoidable negative part about SMT, which is increased difficulty of validation. The only two vendors having execution issues reinforce my belief that over long time, it's a loss. This negates any other advantage from negligible die size gains and big MT improvements.

The issues of memory latency cause the cores to be idle so often that no work gets done on the core for extended periods of time. So, extracting more from the same silicon in highly MT environment (server market) makes sense.

In that sense, since at least AMD, and likely Intel designs are really "server first", that is the motivation.

Maybe Intel's plan was to have a line of E-Core servers for highly MT tasks and than SMT less P-Cores for high ST tasks, except the P-Core did not exactly deliver much in terms of ST. Maybe the goal was faster iteration with SMT-less P-Cores, but now, it seems that market forces are punishing Intel for removing SMT from P-Cores and are not embracing E-Core servers nearly to the extend Intel anticipated.

For Apple M1, as a "client first" design, concentrating on ST makes complete sense...

 

[511]

511, the M5 can go in a PHONE!

Enterprise/Datacenter only companies will die. This is a long term loss. Efficiency comes from constraints(which is a human thing), two of which datacenter loses: Cost and size. This is the history of computing. We're seeing it right now even with AMD and Intel. Phones and Tablets have even bigger of a constraint. RISC vs Intel lost because Intel is used to optimizing for much cheaper, smaller, and much lower power. What the consumer oriented companies do is then they bring that same optimization to datacenter, and kills all datacenter-only companies. Nvidia killed all datacenter graphics companies. The Intel E core team had constraints and under pressure to execute, or be eliminated. The star team P core didn't.

With M4 people said it only beats it in Geekbench because of SME optimization. Now M5 beats it in Cinebench. What's the excuse now? With M3 it beat all laptop processors. Slow, but rather steady.

How about we continue this conversation next gen when everyone will be on N2 than we can compare thee uArches without much noise from the node rn Z5 is on N4P LNC is on N3B/18A same core.

10nm also threw a wrench in Intel's design Schedule GLC was supposed to come out in 2016-17 !! they simply killed themselves

 

[Joe NYC]

@Joe NYC Skill issue. Can't be explained any other way. Also human factors like lack of motivation/hope for future. Lot of the world sees x86 land as no future. Imagine being that engineer. A self fulfilling prophecy where x86 dies not because it can't actually be close enough but people believe it can't be overcome.

I could see this being a factor at Intel, especially their P-Core team, but not at AMD. AMD team is flying high, lots of adrenaline, conquering server and desktop segments. With notebook leadership within eye sight.

Server needs to have a significant modified core then. Because it's a loss everywhere. If it takes 13 months instead of 12, then over 10 years, it's a near full year loss. Glenn Hinton, the architect of Nehalem is quoted as saying "we could have got more performance, but for the sake or mitigating risk, we chose not to". David Kanter of RWT on his Nehalem article said validation is "extremely difficult". So there's always a risk of messing things up seriously, even if you ignore the recent security pitfalls. Or, it takes more time to do it properly. The thing is, you have to do it with every new modification.

SMT vs no SMT can't be compared on ISO basis. I assume the LNC presentation about SMT having significant power and die area disadvantage has to do with big picture, because on the surface it's about adding few extra registers, which is insignificant die area increase.

What about SMT - which requires increased risk and validation times versus no-SMT which does not? How much better is SMT then?

Intel has a chance to demonstrate this with DMR, but it does not seem like it is on a great trajectory.

But there are multiple components that go into making a server chip. The core, even if it benefits from (possibly) faster design cycle can still be held back by other elements, such as process node, IODs etc.

So even if your hypothesis is correct, we will not get a chance to see the proof of it on x86 side.

But maybe on Arm vs. x86 side of things...

 

[511]

Intel has a chance to demonstrate this with DMR, but it does not seem like it is on a great trajectory.

DMR is a giant upgrade over GNR like freaking huge upgrade they have thrown everything at DMR 3D Hybrid Bonding/ 256C/T same memory capacity and bandwidth as Venice Dense
4 New ISA Extension that were standardized

 

[Joe NYC]

511, the M5 can go in a PHONE!

Enterprise/Datacenter only companies will die. This is a long term loss. Efficiency comes from constraints(which is a human thing), two of which datacenter loses: Cost and size. This is the history of computing. We're seeing it right now even with AMD and Intel. Phones and Tablets have even bigger of a constraint.

I think this will be worth revisiting when real first class effort - Intel Clearwater Forest and AMD Zen 6 Dense are on the market.

Because, for the first time, both Intel and AMD are aiming to compete head on with Arm in the server market. I think it is premature write them off.

 

[Hitman928]

Pentium 4 went from 2GHz to 3.2GHz with same power limit and half the die size. The first real brake was with FinFET and Ivy Bridge. Second is GAA.

Of course, there was no doubt circuitry innovation needed to get those gains too, but that also hit the brakes years ago. When Crusoe introduced new circuit innovations, they got less from new process because the new circuit was essentially addressing weaknesses from current process which would be brought with new process anyways.

We had 5V CPUs, but now they are close to the ~0.6V threshold voltage. Easy voltage scaling died with 0.13u, but you still got enormous gains from gate length and capacitance reductions, which died with FinFET. The hobby and power circuitry land is still 5V, 3.3V, and 1.8V, reflecting the history of computing.

Threshold voltages are well below 0.6V now.

 

[BorisTheBlade82]

I think it is rather clear for everyone, that since 2020 Intel and AMD will have established whole Teams to do nothing else than putting Apple's Mx under heavy scrutiny - and in a much more thorough way than CnC etc. al. ever could. They might do profiling as well as optical/physical inspection of the logical as well as the physical design. Of course they can also just hire people from Apple Design which they surely did.
It is quite astonishing, that instead of catching up, the lead seems to still be growing - especially from an efficiency PoV, which should be a high priority for both regarding Server as well as mobile.

 

[511]

I think it is rather clear for everyone, that since 2020 Intel and AMD will have established whole Teams to do nothing else than putting Apple's Mx under heavy scrutiny - and in a much more thorough way than CnC etc. al. ever could. They might do profiling as well as optical/physical inspection of the logical as well as the physical design. Of course they can also just hire people from Apple Design which they surely did.

what's funny is many of Apple's core designers once worked at Intel as for catching up in efficiency i would hold my horses till all of the uArch are on Same Node we are comparing a N3P M5 to a N4P Zen5/N3B LNC

 

[Joe NYC]

DMR is a giant upgrade over GNR like freaking huge upgrade they have thrown everything at DMR 3D Hybrid Bonding/ 256C/T same memory capacity and bandwidth as TURIN Dense
4 New ISA Extension that were standardized

What do you foresee for DMR launch? LBT said there would be a roadmap update, but I don't recall seeing it yet.

 

[511]

What do you foresee for DMR launch? LBT said there would be a roadmap update, but I don't recall seeing it yet.

H2 26 launch similar timeframe as GNR