Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing Raptor Lake-U. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q1 2026.

		Intel Raptor Lake U	Intel Wildcat Lake 15W?	Intel Lunar Lake		Intel Panther Lake 4+0+4
Launch Date		Q1-2024	Q2-2026	Q3-2024		Q1-2026
Model		Intel 150U	Intel Core 7	Core Ultra 7 268V		Core Ultra 7 365
Dies		2	2	2		3
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		Intel 18-A + Intel 3 + TSMC N6
CPU		2 P-core + 8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		4 P-core + 4 LP E-cores
Threads		12	6	8		8
Max Clock		5.4 GHz	?	5 GHz		4.8 GHz
L3 Cache		12 MB		12 MB		12 MB
TDP		15 - 55 W	15 W ?	17 - 37 W		25 - 55 W
Memory		128-bit LPDDR5-5200	64-bit LPDDR5	128-bit LPDDR5x-8533		128-bit LPDDR5x-7467
Size		96 GB		32 GB		128 GB
Bandwidth				136 GB/s
GPU		Intel Graphics	Intel Graphics	Arc 140V		Intel Graphics
RT		No	No	YES		YES
EU / Xe		96 EU	2 Xe	8 Xe		4 Xe
Max Clock		1.3 GHz	?	2 GHz		2.5 GHz
NPU		GNA 3.0	18 TOPS	48 TOPS		49 TOPS

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[Josh128]

AMD's AI GPUs are surprisingly unprofitable. MI300 was selling below corporate average margins a couple quarters ago IIRC. Maybe it's better now...

MI 300 and even MI 355X aint MI 450, and MI 450 and Venice have huge customer contracts waiting on well over 100K units. If Apple has bought up ~40%-50% N2 capacity as is rumored, that doesnt leave a lot of allocation for Nvidia, AMD, and Intel. The most profitable / stock enhancing stuff is coming first, if technically possible.

 

[511]

MI 300 and even MI 355X aint MI 450, and MI 450 and Venice have huge customer contracts waiting on well over 100K units. If Apple has bought up ~40%-50% N2 capacity as is rumored, that doesnt leave a lot of allocation for Nvidia, AMD, and Intel. The most profitable / stock enhancing stuff is coming first, if technically possible.

Intel doesn't need much unlike all the others also TSMC builds capacity on contracts not other way around

 

[Josh128]

Intel doesn't need much unlike all the others also TSMC builds capacity on contracts not other way around

Nova Lake compute silicon isnt insignificant.

 

[511]

Nova Lake compute silicon isnt insignificant.

It is less than AMD's N2 wafer allocation afaik by a decent margin.

 

[Joe NYC]

But they are not perfectly unlimited. If you had 2000 wafers available and you could either make 5 million with them or $750K, which would you choose? Money wins bro, Venice and MI450 are way more profitable than desktop or AMDs still paltry mobile presence. With OpenAI and now Oracle waiting on Helios, Lisa is getting those out first bruh. Consumer PC plebs like you and I will have to wait. Theres zero hurry to get Zen 6 desktop out as they already have the crown with Zen 5/X3D. Consumer GPU market for AMD still tiny, so that takes backseat as well. Share price is what matters, not what we want here to put in our PCs.

AMD may just release V-Cache version of Zen 6 for desktop, sell it for $500 and delay the rest of the line up (if they were in fact short N2 capacity).

Consumer GPUs, as far as RDNA5, were not planned to be on N2.

 

[adroc_thurston]

But they are not perfectly unlimited. If you had 2000 wafers available and you could either make 5 million with them or $750K, which would you choose? Money wins bro, Venice and MI450 are way more profitable than desktop or AMDs still paltry mobile presence. With OpenAI and now Oracle waiting on Helios, Lisa is getting those out first bruh. Consumer PC plebs like you and I will have to wait. Theres zero hurry to get Zen 6 desktop out as they already have the crown with Zen 5/X3D. Consumer GPU market for AMD still tiny, so that takes backseat as well. Share price is what matters, not what we want here to put in our PCs.

AMD and TSM both know how much N2 they need to ramp everything at once.
Stop with this FUD, it's outright embarrassing.

 

[DavidC1]

6233 with 8533 and 6300 with 9600. Xe3 is not at all bottlenecked by memory bandwidth. I would say it's even unusually unaffected by memory bandwidth as the gains should be 3x that to be even at the normal range. Intel could go with 24 Xe3 cores and it would be fine without being bottlenecked.

 

[Joe NYC]

AMD and TSM both know how much N2 they need to ramp everything at once.
Stop with this FUD, it's outright embarrassing.

Normally, it would work that way, but AMD is getting some very large orders, that will need to be put in the oven as soon as beginning of the year (2026), and size of these orders is likely larger than expected.

 

[adroc_thurston]

Normally, it would work that way, but AMD is getting some very large orders, that will need to be put in the oven as soon as beginning of the year, and size of these orders is likely larger than expected.

Stop with the FUD.
It's dumb.

 

[dullard]

Stop with the FUD.
It's dumb.

Says the person who claims no one uses integrated graphics.

 

[Josh128]

Stop with the FUD.
It's dumb.

Whats dumb about it? Maximizing revenue is dumb?

 

[Josh128]

It is less than AMD's N2 wafer allocation afaik by a decent margin.

Well considering AMD has desktop & enterprise CPU and & enterprise GPU, ie a lot of silicon, that doesnt mean its not still a lot of wafers.

 

[adroc_thurston]

Whats dumb about it? Maximizing revenue is dumb?

Maximizing *what* revenue?
AMD builds and ships according to what their short/medium/long-term marketshare targets are.

 

[Joe NYC]

Whats dumb about it? Maximizing revenue is dumb?

I think @adroc_thurston says that because there is a popular urban legend that there is ALWAYS a shortage of capacity for AMD and AMD is always sacrificing something one product over another, continuously re-allocating, juggling wafer allocations.

That part is dumb and has been dumb for ~3+ years.

What is unknown is what happens in the future.

 

[Doug S]

also TSMC builds capacity on contracts not other way around

TSMC isn't like classic Intel where they design fab buildings to be upgradeable across process generations, because foundries keep producing those older nodes for years to come. So they need new fab buildings for new nodes, and the lead time from breaking ground to entering mass production is very large. If they are going to start mass producing N2 by the end of this year they would have had to break ground sometime in 2022 or possibly even earlier. The AI hype hadn't even begun then, let alone inflating as big as it is today.

So it isn't remotely the case that the capacity TSMC built is adequate to handle the initial demand. It is adequate to handle the demand that was prepayed years in advance (which was likely only Apple at any real scale) and their projected demand which would have been based on initial demand for N5 they were producing at the time and the level of demand they were seeing for the (then) upcoming N3. They had no way of knowing at the time they had to make the decision on initial N2 capacity buildout that an AI bubble would cause demand for it to shoot to the moon.

Whatever capacity AMD had booked isn't going to be enough for what they wished they had booked, they are going to have to make decisions about how to allocate the capacity they have, and feeding the AI beast makes the most sense - because once the AI bubble bursts some of those orders will evaporate. Meanwhile they can satisfy the demand for PCs/servers with their existing N3 based stuff a little longer without affecting their sales in that segment much.

 

[adroc_thurston]

I think @adroc_thurston says that because there is a popular urban legend that there is ALWAYS a shortage of capacity for AMD and AMD is always sacrificing something one product over another, continuously re-allocating, juggling wafer allocations.

yes time to stone some people. to death.

Whatever capacity AMD had booked isn't going to be enough for what they wished they had booked, they are going to have to make decisions about how to allocate the capacity they have, and feeding the AI beast makes the most sense - because once the AI bubble bursts some of those orders will evaporate

that's not how any of that works.
There's more than enough N2p for everyone, plus HPC GPGPU sticks are HBM/packaging limited anyway.

 

[Joe NYC]

yes time to stone some people. to death.

that's not how any of that works.
There's more than enough N2p for everyone, plus HPC GPGPU sticks are HBM/packaging limited anyway.

Packaging is catching up, HBM may still be the bottleneck.

Regarding N2P, NVidia is not hogging any of that capacity, so shouldn't really be anything out of ordinary, unless AMD wants to hog more capacity than already ordered...

 

[adroc_thurston]

Packaging is catching up

lol

Regarding N2P, NVidia is not hogging any of that capacity, so shouldn't really be anything out of ordinary, unless AMD wants to hog more capacity than already ordered...

again, GPGPU stuff is not eating wafers.

 

[dullard]

Please move AMD wafer discussion to a different thread. It probably would be important to include in that discussion the OpenAI order this week. Otherwise, everything discussed is seriously out-of-date.

 

[Josh128]

Maximizing *what* revenue?

Their most potentially lucrative revenue. Revenue from enterprise AI hardware, Venice and MI 450.

AMD builds and ships according to what their short/medium/long-term marketshare . targets are.

Exactly why Venice and MI 450 are launching first, lol. AMD had no idea they would get the OpenAI and Oracle MI 450 contracts announced in the past two weeks when they secured 2nm supply years ago, yet Venice was still their first 2nm product. Now that they have two giant new contracts you somehow think they will slow their roll and push out desktop Zen 6 first? We can revisit at the end of next summer to see if desktop Zen 6 launches before Venice or MI 450 like you are claiming.

 

[adroc_thurston]

Their most potentially lucrative revenue. Revenue from enterprise AI hardware, Venice and MI 450.

Again, maximizing *what*.
There's a fixed amount of stuff they can sell into DC channels, way below the N2 allocation they can actually muster.

Exactly why Venice and MI 450 are launching first, lol

Launch yes, DC product ramp takes a while.

AMD had no idea they would get the OpenAI and Oracle MI 450 contracts announced in the past two weeks when they secured 2nm supply years ago,

YES THEY DID.
Those are long-term, multi-year roadmap commitments.

Now that they have two giant new contracts you somehow think they will slow their roll and push out desktop Zen 6 first? We can revisit at the end of next summer to see if desktop Zen 6 launches before Venice or MI 450 like you are claiming.

man this is just embarassing.

 

[Joe NYC]

Their most potentially lucrative revenue. Revenue from enterprise AI hardware, Venice and MI 450.

Exactly why Venice and MI 450 are launching first, lol. AMD had no idea they would get the OpenAI and Oracle MI 450 contracts announced in the past two weeks when they secured 2nm supply years ago, yet Venice was still their first 2nm product.

It was known (and leaked) for a long time that Mi450 would be on N2.

There was a leak of which company and which product were in earliest silicon test runs and how many wafers. Both Mi450 and Zen 6 were on that list.

Intel was also on the list, even before it was known which product it would be. Turned out to be Nova Lake.

 

[OneEng2]

That's also how they fell behind: they took big risks.

LOL. I have been following this dance for decades .

I would argue they fell behind by failing to move to EUV quickly enough and trying to make DUV's square peg fit in a round hole.

They certainly made many other architectural mistakes and business blunders, but per the process discussion, I think it was purely arrogance. Intel had lead the industry for so long they got caught sitting on their laurels. By the time it was obvious to the most casual observer ..... well, here we are .

I think @adroc_thurston says that because there is a popular urban legend that there is ALWAYS a shortage of capacity for AMD and AMD is always sacrificing something one product over another, continuously re-allocating, juggling wafer allocations.

That part is dumb and has been dumb for ~3+ years.

What is unknown is what happens in the future.

I haven't seen any evidence in either direction. It would be great if someone could post something vs. simply demanding their POV is correct "because it is".

that's not how any of that works.
There's more than enough N2p for everyone, plus HPC GPGPU sticks are HBM/packaging limited anyway.

Yea, because new nodes on the cutting edge always have unlimited capacity?

FYI, "the way it works" is called "supply and demand". Either everyone and their brother can get all the N2P they want, and it is pretty inexpensive OR there is a constraint on how many N2P wafers can be produced and the price is raised until the demand reaches the ability of the supply.

You can't have it both ways. ECON 101.

 

[adroc_thurston]

because new nodes on the cutting edge always have unlimited capacity?

TSM tends to build big yes.
There's a good reason they're at >90% bleeding edge foundry share.

Either everyone and their brother can get all the N2P they want, and it is pretty inexpensive

Guess what

 

[Kepler_L2]

[X86] Add support for Nova Lake by mikolaj-pirog · Pull Request #163552 · llvm/llvm-project

Add support for Nova Lake, per Intel Architecture Instruction Set Extensions Programming Reference rev. 59 (https://cdrdv2.intel.com/v1/dl/getContent/671368)

github.com

Did Intel remove APX/AVX10 from NVL or am I missing something?