Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing Raptor Lake-U. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q1 2026.

		Intel Raptor Lake U	Intel Wildcat Lake 15W?	Intel Lunar Lake		Intel Panther Lake 4+0+4
Launch Date		Q1-2024	Q2-2026	Q3-2024		Q1-2026
Model		Intel 150U	Intel Core 7	Core Ultra 7 268V		Core Ultra 7 365
Dies		2	2	2		3
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		Intel 18-A + Intel 3 + TSMC N6
CPU		2 P-core + 8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		4 P-core + 4 LP E-cores
Threads		12	6	8		8
Max Clock		5.4 GHz	?	5 GHz		4.8 GHz
L3 Cache		12 MB		12 MB		12 MB
TDP		15 - 55 W	15 W ?	17 - 37 W		25 - 55 W
Memory		128-bit LPDDR5-5200	64-bit LPDDR5	128-bit LPDDR5x-8533		128-bit LPDDR5x-7467
Size		96 GB		32 GB		128 GB
Bandwidth				136 GB/s
GPU		Intel Graphics	Intel Graphics	Arc 140V		Intel Graphics
RT		No	No	YES		YES
EU / Xe		96 EU	2 Xe	8 Xe		4 Xe
Max Clock		1.3 GHz	?	2 GHz		2.5 GHz
NPU		GNA 3.0	18 TOPS	48 TOPS		49 TOPS

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[Joe NYC]

I haven't seen any evidence in either direction. It would be great if someone could post something vs. simply demanding their POV is correct "because it is".

Demand tanked in ~2022 and TSMC had plenty of spare as result of order cancellations and rescheduling of deliveries.

But like a broken record, the "trade-off" crowd never changed their tune for one second. AMD (and no other company) is always short of capacity, according to this urban legend, even in the middle of a glut, and has to juggle wafer starts.

And this discussion is completely separate from the real situation: You get all the capacity that you contract for, from TSMC. Even if you no longer want it, in which case there may be cancellation penalties.

IIRC, Intel was, according to some rumors, in this situation, when Intel had a lot of N3B capacity on order, under contract, and Intel was not ready to use all the wafers ordered at the time the wafers were scheduled to be produced.

The capacity has tightened in last 6-9 months, especially on N5 node while there was underutilization on N7. Apparently, TSMC responded to it by converting some N7 capacity to N4/N5.

Speaking of TSMC, they have their quarterly report late tonight, which is morning Taiwan time.

 

[511]

[X86] Add support for Nova Lake by mikolaj-pirog · Pull Request #163552 · llvm/llvm-project

Add support for Nova Lake, per Intel Architecture Instruction Set Extensions Programming Reference rev. 59 (https://cdrdv2.intel.com/v1/dl/getContent/671368)

github.com

Did Intel remove APX/AVX10 from NVL or am I missing something?

No

 

[Kepler_L2]

No

Why are they not featured in either the LLVM patch or Intel's documentation then?

 

[511]

Why are they not featured in either the LLVM patch or Intel's documentation then?

Cause they are just getting started afaik for the NVL

 

[Josh128]

YES THEY DID.

No they didnt. They *hoped* to take market share from Nvidia with those product designs. They didnt know they would land these specific deals.

Those are long-term, multi-year roadmap commitments.

Yes. And roadmap does not guarantee sales or contracts.

man this is just embarassing.

It kind of is. When Venice pre-empts desktop next year, I'll be back here to remind you of that. Validation time is the only reason is might not.

 

[MoistOintment]

The point is that there's a lead time for wafer orders. It's not that TSMC may be physically incapable of providing volume to AMD, but rather AMD underestimated their own wafer requirements when they placed the order / reservation years in advance.

IF AMD got a lucrative contract with OpenAI after they placed orders to for N2, then their N2 allocation order may not be sufficient initially to meet those contractual obligations and early launch Zen 6 desktop.

It really depends on:
1) Did AMD consider this OpenAI partnership when reserving N2 capacity
2) If they need to increase their N2 purchase, what's the lead time on that? Can they add additional N2 capacity immediately or is there a delay to it?

I don't think it's unreasonable to assess the possibility that AMD's OpenAI deal came after their initial N2 order and that servicing that contract may cause delays to less important product lines that can wait until additional capacity is available to service it.

It's not really a question of whether or not TSMC can physically meet AMD's demand: It's if AMD correctly estimated their demand in advance and how long it takes to add more wafers if necessary.

 

[511]

we are slightly moving off topic lol

 

[adroc_thurston]

They *hoped* to take market share from Nvidia with those product designs

You don't hope for anything.

And roadmap does not guarantee sales or contracts

YES THEY DO.
You sell the roadmap, not the parts themselves.

When Venice pre-empts desktop next year, I'll be back here to remind you of that

Venice volume crossover with Turin is like q3'27.
Idk what's even your point.

but rather AMD underestimated their own wafer requirements

Yes they're all incompetent lobotomized cretins that can't even model their own volume!
And you're a genius.

 

[MoistOintment]

Yes they're all incompetent lobotomized cretins that can't even model their own volume!
And you're a genius.

Considering Epyc's constant backorder status, I'd say yes, they did underestimate their demand. It's clearly obvious in Enterprise Supply channels.

I wouldn't call it "incompetence" to find out your product is more in demand then expected because your competitor's offerings were delayed and less competitive than expected.

 

[adroc_thurston]

Considering Epyc's constant backorder status,

no issues there.

It's clearly obvious in Enterprise Supply channels.

nope.

I wouldn't call it "incompetence" to find out your product is more in demand then expected because your competitor's offerings were delayed and less competitive than expected.

GNR was mostly on time and mostly on target.

 

[511]

GNR was mostly on time and mostly on target.

GNR is being held back by a RWC+ it's Golden cove+ can't believe Intel used 3 gens of Golden cove to compete against Zen3-5 🤣

 

[adroc_thurston]

GNR is being held back by a RWC+ it's Golden cove+ can't believe Intel used 3 gens of Golden cove to compete against Zen3-5 🤣

L3 perf is also stinky, even for the local tile.

 

[511]

L3 perf is also stinky, even for the local tile.

It's been like that for a while as far as I can remember

 

[OneEng2]

TSM tends to build big yes.
There's a good reason they're at >90% bleeding edge foundry share.

One of the most incorrect statements I have heard from you ever (and that is saying quite a lot).

"Bleeding edge" being "inexpensive" is nearly as incorrect as "Bleeding edge" being "unlimited".

It kind of is. When Venice pre-empts desktop next year, I'll be back here to remind you of that. Validation time is the only reason is might not.

Now, this actually makes sense. Since Venice is a very high margin product, it would make perfect sense for AMD to introduce N2 with Venice so they can work out the lower yield early production while not taking a financial bath.

This also works out because Venice volume will be orders of magnitude lower volume than desktop or mobile.

I think I would have to bet on your side on this one .

 

[inquiss]

One of the most incorrect statements I have heard from you ever (and that is saying quite a lot).

"Bleeding edge" being "inexpensive" is nearly as incorrect as "Bleeding edge" being "unlimited".

Now, this actually makes sense. Since Venice is a very high margin product, it would make perfect sense for AMD to introduce N2 with Venice so they can work out the lower yield early production while not taking a financial bath.

This also works out because Venice volume will be orders of magnitude lower volume than desktop or mobile.

I think I would have to bet on your side on this one .

Ofc Venice will be low volume to start, it takes a while to ramp. Look how long it takes each generation to ramp to sales. Contracts take time etc etc.

That's completely unrelated to the fact they book a lot of wafers in advance.

 

[511]

DC are slower to ramp than client

 

[adroc_thurston]

"Bleeding edge" being "inexpensive" is nearly as incorrect as "Bleeding edge" being "unlimited

Yeah it's cheap.
A perk of high volumes and good yields.

it would make perfect sense for AMD to introduce N2 with Venice so they can work out the lower yield early production while not taking a financial bath

What lower yield this is TSM.
Not Intel or Samsung.

 

[511]

Not Intel or Samsung.

Intel doesn't have low yields Samsung struggle is on their latest processor they are able too yield 5nm just fine.

 

[adroc_thurston]

Intel doesn't have low yields

Yeah they do.

Samsung struggle is on their latest processor they are able too yield 5nm just fine.

7LPP/5LPE yields we're awful on ramp.

 

[oak8292]

As long as everybody is discussing wafer supply and capacity you may as well throw in HBM supply and packaging supply which is short for both Nvidia and AMD.

Intel got packaging contracts due to packaging shortages at TSMC.

Micron is a great investment because they have sold out HBM.

AMD got burned at GF with wafer contracts and it seems to me they would rather be short than long. They need margin and over supplying product is a good way to burn margin. Intel’s balance sheet has been stronger than AMDs for a really long time and they couldn’t afford a price war. AMD could be contracting for ‘excess’ wafers as we speak as relative balance sheet strength shifts.

 

[511]

Yeah they do.

No they don't their D0 is in good shape and parametric is fine

7LPP/5LPE yields we're awful on ramp.

They are not now

 

[OneEng2]

Yeah it's cheap.
A perk of high volumes and good yields.

Not sure what reality you live in. You consider N2 a "cheap" node eh?

 

[adroc_thurston]

No they don't their D0 is in good shape and parametric is fine

Which is why PTL is behind schedule and 300MHz down on fmax?

 

[OneEng2]

Which is why PTL is behind schedule and 300MHz down on fmax?

If true, then it is likely due to hot spots in BSPDN on 18A ..... so yea, yields at higher clocks.

 

[adroc_thurston]

If true, then it is likely due to hot spots in BSPDN on 18A

You're not getting hotspots at Intel core densities.