Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

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Tigerick

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Apr 1, 2022
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Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

Intel Alder Lake - NIntel Wildcat LakeIntel Lunar LakeMediatek D9500
Launch DateQ1-2023Q2-2026 ?Q3-2024Q3-2025
ModelIntel N300?Core Ultra 7 268VDimensity 9500 5G
Dies2221
NodeIntel 7 + ?Intel 18-A + TSMC N6TSMC N3B + N6TSMC N3P
CPU8 E-cores2 P-core + 4 LP E-cores4 P-core + 4 LP E-coresC1 1+3+4
Threads8688
Max Clock3.8 GHz?5 GHz
L3 Cache6 MB?12 MB
TDP7 WFanless ?17 WFanless
Memory64-bit LPDDR5-480064-bit LPDDR5-6800 ?128-bit LPDDR5X-853364-bit LPDDR5X-10667
Size16 GB?32 GB24 GB ?
Bandwidth~ 55 GB/s136 GB/s85.6 GB/s
GPUUHD GraphicsArc 140VG1 Ultra
EU / Xe32 EU2 Xe8 Xe12
Max Clock1.25 GHz2 GHz
NPUNA18 TOPS48 TOPS100 TOPS ?






PPT1.jpg
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As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



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OneEng2

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gdansk said:
I do not have to admire it nor follow the delusions of Skymont messianic cult. It's Zen 4 but without the ability to clock high nor support AVX-512 instructions a few years later on a better process.
Click to expand...
One on one, Zen 6c will most certainly overpower Darkmont IMO. Everyone keeps calling foul on SIMD instruction use and SMT. Seems fair to me. Use what you got in your architecture .... and lots of programs do. I can't buy into the idea that you have to benchmark E cores where they work best.
gdansk said:
It will prove delusional. The ILP wall comes for all its descendants all the same. And at the end of the day Skymont will always be Skymont, not its children.
Click to expand...
The thing I keep coming back to is that should you add good SIMD support, SMT, and all the associated plumbing needed to do those things, Skymont would likely look much more like a P core does today.
gdansk said:
18A CWF Darkmont is about 25% more cores in given area than N3E Turin D Z5C when excluding LLC.
Good enough. Seems it all comes down to clocks.
Click to expand...
Considering that there is an expected 20% transistor density improvement going from N3E to N2, seems likely that Darkmont might be about the same size as Zen 6c. While Darkmont is going to have AVX10, it is only going to support a 256 bit data path vs Zen 6c's full 512 bit data path. So while it will do better (much better) than Skymont, it is likely going to get seriously beaten about the head and shoulders by Zen 6c in real-world workloads IMO.

Just the lack of SMT will leave Darkmont at a 40% per core deficit to Zen 6. With this kind of deficit, it's going to take a lot more than 288 darkmont cores to best the 256 core Venice D (Zen 6c) IMO.
 
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511

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OneEng2 said:
Considering that there is an expected 20% transistor density improvement going from N3E to N2, seems likely that Darkmont might be about the same size as Zen 6c
Click to expand...
You are dead wrong on this one the area is roughly the same between Skymont and darkmont for 1.1mm2 Core+L1 and Turin Dense to Venice Dense should keep the area same imo they are not doing a big node shrink.
 
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Kepler_L2

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Sep 6, 2020
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511 said:
You are dead wrong on this one the area is roughly the same between Skymont and darkmont for 1.1mm2 Core+L1 and Turin Dense to Venice Dense should keep the area same imo they are not doing a big node shrink.
Click to expand...
What's Zen5C size on Turin-D?
 
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511

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The base Dies are ~350mm2 for Clearwater quite smaller than ~598mm2 GNR Die and the 18A chiplets are 55mm2
 
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511

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Intel need a good L3 Team they cooked the fabric in ARL/MTL. GNRs was slow and looks like Clearwater Forest is not enough to overcome the BW Bottleneck.
 
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gdansk

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Doug S said:
That a high end product selling for a premium price, so packaging cost is much less of a factor. Plus each CCD has 8 Zen 5 or 16 Zen 5c cores so it is much much larger than the tiny little one core dies Intel is using. Totally different economics.
Click to expand...
Oh, no, maybe something was missed here. This is a server chip being discussed in the Lakes thread for some reason. It's 12 x 24 core dies. The dies are tiny because Darkmont is indeed pretty small when the LLC is in another castle.
 
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lightisgood

Senior member
May 27, 2022
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511 said:
Intel need a good L3 Team they cooked the fabric in ARL/MTL. GNRs was slow and looks like Clearwater Forest is not enough to overcome the BW Bottleneck.
Click to expand...

CWF's cache-arch is not clear yet.
For example, I don't know how much there are mesh-stops in a compute-tile, you too.
 
coercitiv

coercitiv

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Jan 24, 2014
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Doug S said:
That a high end product selling for a premium price, so packaging cost is much less of a factor. Plus each CCD has 8 Zen 5 or 16 Zen 5c cores so it is much much larger than the tiny little one core dies Intel is using. Totally different economics.
Click to expand...
Turin is obviously cheaper to package but we're still looking at 16 chiplets for the vanilla cores and 12 chiplets for dense. The Intel tiles also lack L3 as @gdansk already mentioned.

That being said, Intel has this tradition of never adopting the straightforward approach of the competition. With the P cores they insist on those huge tiles, with the E cores they went the opposite way of breaking everything into multiple small pieces. The only thing constant about an Intel product is cost, they're always expensive to make. :p

PS: imagine if Intel had a tile strategy on the consumer side that would allow them to plant one of these 55mm2 Darkmont tiles in a desktop product. Too much sense? /s
 
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Doug S

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gdansk said:
Oh, no, maybe something was missed here. This is a server chip being discussed in the Lakes thread for some reason. It's 12 x 24 core dies. The dies are tiny because Darkmont is indeed pretty small when the LLC is in another castle.
Click to expand...

Ah, I missed the mention of "Xeon" in the last line of the bullet points that mentioned the 12 chiplets. I gave up years ago even trying to keep Intel's stupid code names straight. Since people were talking about that Panther Lake chip made on 18A for industrial type markets that was recently released, I thought that's what this was!

Glad to know the world hasn't gone crazy without me noticing and Intel isn't building chips with single core chiplets!
 
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511

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Yeah the Mesh stops are not clear but they will be 24 For the cores+ 4 for IMC + 2/4 For EMIB?
 
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511

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PTL won't have this L3 Issues cause there are only 6 Ring Stops for the Cores and 1 For IMC I guess.
 
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