Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[Geddagod]

No wonder they moved to even smaller chiplet with DMR/Clearwater Forest.
18A dies at 55mm2 and L3/Mesh Intel 3-T at 350mm2

https://twitter.com/x/status/1862509554736800177

DMR tiles are rumored to be big, no? I expect each tile to easily be above 300mm2 each.
The real interesting part is that Venice is also rumored to be moving to bigger tiles on N2, or at least the dense variants of it.

 

[511]

DMR tiles are rumored to be big, no? I expect each tile to easily be above 300mm2 each.
The real interesting part is that Venice is also rumored to be moving to bigger tiles on N2, or at least the dense variants of it.

Nope From my hypothesis DMR will reuse these tiles but swap out the core+L2 in favour Panther Cove for 16P core tiles each replacing 24E core tile.
So to make
For a maximum of 16*4 = 64 c per tile and than 4 Intel 3T base tile each containing 4 memChannel(not meme channel)
They can make


3*16*4 = 192C DMR SKU using 16ch
4*16*4 = 256C DMR SKU 16ch
3*16*2 = 96C SKU 8 Ch
4*16*2 = 128C SKU 8Ch


The format is 18AP tiles*Cores*base tiles on 3T
That's just my guess but it gives them quite flexibility and IP reuse between Clearwater Forest/DMR/RRF for the compute part the IO Tiles are Intel 4/3 though for DMR

 

[Geddagod]

Nope From my hypothesis DMR will reuse these tiles but swap out the core+L2 in favour Panther Cove for 16P core tiles each replacing 24E core tile.
So to make
For a maximum of 16*4 = 64 c per tile and than 4 Intel 3T base tile each containing 4 memChannel(not meme channel)
They can make
3*16*4 = 192C DMR SKU using 16ch
4*16*4 = 256C DMR SKU 16ch
2*16*4 = 96C SKU 8 Channel
That's just my guess

I was going off this diagram
Which Bionic said wasn't fully correct, sure, but then also said the core count was different (256 cores). I expect the tile config to be the same.

I also don't think DMR and CLF are the same "CPU family", for the tiles to be that interchangeable.

 

[511]

I was going off this diagram
View attachment 128954Which Bionic said wasn't fully correct, sure, but then also said the core count was different (256 cores). I expect the tile config to be the same.

I also don't think DMR and CLF are the same "CPU family", for the tiles to be that interchangeable.

This DDR part is incorrect the Memory Channel are on Intel 3 base die not on IO die and the 4 Tiles are made of smaller 18AP tiles below them.

 

[511]

I also don't think DMR and CLF are the same "CPU family", for the tiles to be that interchangeable.

They are the base die that contains L3/Mesh and IMC it's not that difficult if you think about it.

 

[DavidC1]

Clearwater Forest is socket compatible with Sierra Forest and part of the Birch Stream platform. DMR is next gen platform.

 

[511]

Clearwater Forest is socket compatible with Sierra Forest and part of the Birch Stream platform. DMR is next gen platform.

I always read Birch as Bi*ch stream platform

 

[igor_kavinski]

I always read Birch as Bi*ch stream platform

Pretty sure the engineers are calling it that internally.

 

[DrMrLordX]

Also let's not forget that ARL-U mobile chips are basically MTL-U on Intel 3. And Fab34 is not fully completed construction per Intel's 10K. I think that refers to tooling & not shell construction. it's only partially equipped with tools. I am also pretty sure Intel 4 line is same as Intel 3. So other MTL chips are also being fab'ed in there. So Intel 4/Intel 3 is capacity constrained!

Yeah, good catch, sometimes I forget about Arrow Lake-U (which, as a product, only exists to be a cheap alternative to Lunar Lake I guess?). Oh the sadness of Intel being potentially-unable to make an Intel 3 stopgap desktop chip due to demand for Arrow Lake-U. Though to be honest, I have no idea how many units of Arrow Lake-U are actually moving out there.

 

[511]

Not much corps are buying RPL-U it will shift to WCL-U later

 

[igor_kavinski]

Oh the sadness of Intel being potentially-unable to make an Intel 3 stopgap desktop chip due to demand for Arrow Lake-U. Though to be honest, I have no idea how many units of Arrow Lake-U are actually moving out there.

Yes, I feel that sadness deep inside me too.

I can see few HP and Dell 265U and 255U models available on my local Amazon. All priced way too high compared to RPL-U so they won't sell much.




Only a numbskull would opt for the 255U laptop with such a massive price difference ($346).

 

[511]

Yes, I feel that sadness deep inside me too.

I can see few HP and Dell 265U and 255U models available on my local Amazon. All priced way too high compared to RPL-U so they won't sell much.

View attachment 128976
View attachment 128977

Only a numbskull would opt for the 255U laptop with such a massive price difference ($346).

Windows 11 Pro vs Home but -512GbB SSD for ARL-U vs Ryzen AI lol definitely not worth it

 

[poke01]

Yes, I feel that sadness deep inside me too.

I can see few HP and Dell 265U and 255U models available on my local Amazon. All priced way too high compared to RPL-U so they won't sell much.

View attachment 128976
View attachment 128977

Only a numbskull would opt for the 255U laptop with such a massive price difference ($346).

laptops costing >$1600AUD(~AED4000) should also have a minimum 1440p screen so text is sharp. 16:10 or 3:2 is good too but come on increase the res.

 

[Magio]

Yes, I feel that sadness deep inside me too.

I can see few HP and Dell 265U and 255U models available on my local Amazon. All priced way too high compared to RPL-U so they won't sell much.

View attachment 128976
View attachment 128977

Only a numbskull would opt for the 255U laptop with such a massive price difference ($346).

I'm not gonna say Intel's recent stuff isn't typically more expensive than AMD's, but this is comparing a ProBook (targeting enterprise) with an entry level Omnibook, they're not targeting the same segment at all. Here on Anandtech forums we look at specs first but the actual laptop market has a lot more differentiators than what CPU it runs on.

My general rule of thumb is that "enterprise" laptops support are always overpriced compared to their consumer counterparts, unless they come with enterprise level warranty and support.

 

[igor_kavinski]

I'm not gonna say Intel's recent stuff isn't typically more expensive than AMD's, but this is comparing a ProBook (targeting enterprise) with an entry level Omnibook, they're not targeting the same segment at all. Here on Anandtech forums we look at specs first but the actual laptop market has a lot more differentiators than what CPU it runs on.

My dumb IT guy would buy the overpriced enterprise laptop 10 times out of 10, not because the enterprise features are necessary but because Intel. If the prices and CPUs were reversed (cheaper Intel Omnibook and expensive Ryzen ProBook), he would get the Omnibook. There's a reason why I think of such people as absolute morons with just enough functioning neurons to fake it as fit for the job. Enterprise features matter only to companies buying lots of laptops in bulk for their workforce.

 

[511]

Just found something even more shocking.Ingel really did beef up the IMC in ARL

 

[fastandfurious6]

nova lake 3d cache confirmed? TSMC?

 

[511]

Not 3D but large cache and TAMC N2

 

[OneEng2]

Those are gigantic dies, I didnt realise they were that huge. No wonder AMD is destroying them in profit per CPU.

Intel needs to get their mesh latencies down and move to smaller tiles/chiplets. That really is a big die.

The real interesting part is that Venice is also rumored to be moving to bigger tiles on N2, or at least the dense variants of it.

Current Turin D (16c) Zen5c is ~ 84mm^2 on N3E. If you double that on N3E you get 168mm^2. Now shrink it ~20% for N2 and you get about 130mm^2.... so yes, bigger, but still quite manageable.

 

[511]

Current Turin D (16c) Zen5c is ~ 84mm^2 on N3E. If you double that on N3E you get 168mm^2. Now shrink it ~20% for N2 and you get about 130mm^2.... so yes, bigger, but still quite manageable.

Venice dense is 32C/64T per CCX from the rumors

 

[OneEng2]

Venice dense is 32C/64T per CCX from the rumors

As opposed to Turin D at 16c/32t per CCX. Thus I doubled the size from 84 to 168 (What Venice D would be on N3E), then shrunk it down based on the transistor density increase of going to N2.

 

[Geddagod]

As opposed to Turin D at 16c/32t per CCX. Thus I doubled the size from 84 to 168 (What Venice D would be on N3E), then shrunk it down based on the transistor density increase of going to N2.

I don't think one should include the 20% shrink from N3 to N2, since I doubt AMD doesn't increase the "architectural" area of the core itself. I don't think core area or CCX area iso core count will change significantly.
But also, Turin Dense saves a good chunk of area because it halves the L3 capacity per core, which Venice Dense reverses.
I agree with your overall sentiment though, the CCD area won't be massive or anything. I think above 150mm2 is a safe guess.

 

[511]

As opposed to Turin D at 16c/32t per CCX. Thus I doubled the size from 84 to 168 (What Venice D would be on N3E), then shrunk it down based on the transistor density increase of going to N2.

You are assuming core area won't be increasing which ain't going to happen also 4X L3 which didn't Shrink

 

[Kepler_L2]

I don't think one should include the 20% shrink from N3 to N2, since I doubt AMD doesn't increase the "architectural" area of the core itself. I don't think core area or CCX area iso core count will change significantly.
But also, Turin Dense saves a good chunk of area because it halves the L3 capacity per core, which Venice Dense reverses.
I agree with your overall sentiment though, the CCD area won't be massive or anything. I think above 150mm2 is a safe guess.

Zen6 core area is quite small, even smaller than Zen4

 

[Joe NYC]

Not much corps are buying RPL-U it will shift to WCL-U later

When is that expected to be released?