Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing Raptor Lake-U. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q1 2026.

		Intel Raptor Lake U	Intel Wildcat Lake 15W?	Intel Lunar Lake		Intel Panther Lake 4+0+4
Launch Date		Q1-2024	Q2-2026	Q3-2024		Q1-2026
Model		Intel 150U	Intel Core 7	Core Ultra 7 268V		Core Ultra 7 365
Dies		2	2	2		3
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		Intel 18-A + Intel 3 + TSMC N6
CPU		2 P-core + 8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		4 P-core + 4 LP E-cores
Threads		12	6	8		8
Max Clock		5.4 GHz	?	5 GHz		4.8 GHz
L3 Cache		12 MB		12 MB		12 MB
TDP		15 - 55 W	15 W ?	17 - 37 W		25 - 55 W
Memory		128-bit LPDDR5-5200	64-bit LPDDR5	128-bit LPDDR5x-8533		128-bit LPDDR5x-7467
Size		96 GB		32 GB		128 GB
Bandwidth				136 GB/s
GPU		Intel Graphics	Intel Graphics	Arc 140V		Intel Graphics
RT		No	No	YES		YES
EU / Xe		96 EU	2 Xe	8 Xe		4 Xe
Max Clock		1.3 GHz	?	2 GHz		2.5 GHz
NPU		GNA 3.0	18 TOPS	48 TOPS		49 TOPS

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[igor_kavinski]

AMD Ryzen 7 9800X3D workstation test: Is it mean or does it just want to play? | Part 2 of 2 | Page 7 | igor´sLAB

Gaming was yesterday, in the truest sense of the word. I’ve linked yesterday’s article with the gaming benchmarks below. Today we finally have something for the working people, who of course also like…

www.igorslab.de

Cheer up, gloomy Intel folks!

Pat's confused CPU team managed to create at least one SKU that wins the efficiency crown in at least ONE benchmark

 

[DavidC1]

Why is this?

ARL-U is Meteorlake ported to Intel 3.

 

[511]

AMD Ryzen 7 9800X3D workstation test: Is it mean or does it just want to play? | Part 2 of 2 | Page 7 | igor´sLAB

Gaming was yesterday, in the truest sense of the word. I’ve linked yesterday’s article with the gaming benchmarks below. Today we finally have something for the working people, who of course also like…

www.igorslab.de

Cheer up, gloomy Intel folks!

Pat's confused CPU team managed to create at least one SKU that wins the efficiency crown in at least ONE benchmark

View attachment 111852

If you remove dlvr the MT power efficiency increases drastically though u have to give skymont team the credit its just they make worse decision again and again probably some product manager

 

[adroc_thurston]

If you remove dlvr the MT power efficiency increases drastically

No, you're just moving pdn losses elsewhere.

 

[DavidC1]

No, you're just moving pdn losses elsewhere.

Why? Bypassing DLVR means under load you don't have the losses due to going through the linear regulator.

 

[Hulk]

No, it is not my own rig, a friend wanted to build a new machine (he is still on a 6700K,1070Ti) and I convinced him to buy Arrow Lake, what a good friend I am I know. While assembling the machine I ran some benches.

You ARE a good friend. We all know that when you build a rig or even suggest what to buy you're on the hook for tech support for the life of the product!

 

[Hulk]

ARL-U is Meteorlake ported to Intel 3.

That is a letdown. I guess Intel 3 doesn't have the transistor density for Lion Cove and Skymont to make it economically feasible.

 

[adroc_thurston]

I guess Intel 3 doesn't have the transistor density for Lion Cove and Skymont to make it economically feasible.

It's just a minimal effort refresh for mainstream (well, as mainstream as MTL can get).

 

[511]

The refresh may be more intresting as we can compare I3 vs I4 on an same architecture to understand the gain of the process of the die is roughly 5% smaller from the nodes public info

 

[DavidC1]

That is a letdown. I guess Intel 3 doesn't have the transistor density for Lion Cove and Skymont to make it economically feasible.

It's basically to fill the low price segment that Lunarlake can't fill.

It looks like based on clocks it should be solid 20% faster in MT which is decent.

It‘s not good compare to 8845,but not bad for U15.

It's not too good price wise either.

Certainly not compared to the days when they could use a 80mm2 dual core die that is branded up to Core i3 and sold in tens of millions. Now you have packaging costs on top of needing various sized dies, one which is big as a single die back then.

Of course compared to Lunarlake it might be cheap, but that's not saying much. To the finance company known as "Intel" it's basically choosing between urine and feces to step on.

 

[511]

That is a letdown. I guess Intel 3 doesn't have the transistor density for Lion Cove and Skymont to make it economically feasible.

I don't think that's the reason it's HP Libraries (3-3) which are pretty much on par in between nodes(Intel 3 and N3E) as for LNC it is a regression vs RWC in some areas for skymont you have to ask intel cause it would have been on par with N3B
as for cheaper option it would be fine for the 800$ market

 

[LightningZ71]

With 2-300mhz boost improvement, it should be about 5% better in single core benchmarks too. The E cores boost speeds, notably all-core boosts are up a good bit. It remains to be seen if they raised the ring bus speeds as they were quite low on OG Meteor Lake as they could be an issue for the MT scores...

 

[511]

The biggest improvements are base speed with the boost speed can't show their worth due to OEMs bad practices like cheaping out on paste Optimizations

 

[Hulk]

I don't think that's the reason it's HP Libraries (3-3) which are pretty much on par in between nodes(Intel 3 and N3E) as for LNC it is a regression vs RWC in some areas for skymont you have to ask intel cause it would have been on par with N3B
as for cheaper option it would be fine for the 800$ market

Losing Lion Cove isn't a big deal but not including Skymont is a big hit in performance.

 

[LightningZ71]

Even at the improved density (if any) that Intel3 brings, there wouldn't be physically enough room on the package substrate to fit a die large enough to hold 8 Skymont cores with the required P cores. Also, consider that part of why Arrow Lake is so dependent on the performance of Skymont is that Lion Cove doesn't have HT enabled. The P cores on Meteor lake DO have HT. Faster E cores coupled with faster P cores will make a notable difference in MT.

 

[dttprofessor]

Losing Lion Cove isn't a big deal but not including Skymont is a big hit in performance.

For CCG ,intel 3 is a expensive node.
For Pat , intel 3 is good.

 

[511]

Losing Lion Cove isn't a big deal but not including Skymont is a big hit in performance.

Exactly i agree

 

[511]

For CCG ,intel 3 is a expensive node.
For Pat , intel 3 is good.

For intel as a whole it is a cheaper node also Skymont stated with N3 in mind I don't think they ever thought Intel 3 would be so good as it is rn when starting in 2020-21 planning for ARL

 

[OneEng2]

Seems like an awful lot of tap dancing going on over at Intel.

 

[adroc_thurston]

Skymont stated with N3 in mind

It's a portable core made with industry standard EDA tools. There's no "node in mind".

 

[Josh128]

It's a portable core made with industry standard EDA tools. There's no "node in mind".

All modern cores are definitely designed with node in mind, regardless of portability to other nodes.

 

[SiliconFly]

.

 

[511]

It's a portable core made with industry standard EDA tools. There's no "node in mind".

Yes but during the start phase it was with N3 and no one at intel knew about the future of the nodes and they would turn to be better

 

[adroc_thurston]

All modern cores are definitely designed with node in mind, regardless of portability to other nodes.

No.
Intel picked N3 because it was the best node available. That's it!

Even though it's portable (node agnostic), it still takes a significant amount of (engineering) effort, time & money to fab it in a new node

Nope, someone like ARM serves reference physical implementations yearly for a whole bunch of cores, for a pile of very different nodes.

 

[SiliconFly]

.