Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[511]

N2 with GAA goes HVM in H2 2025.

You know from historical trends that Apple gets a year of exclusivity from new TSMC Process not iterations So N3B entered in HVM in H2 22 we got it in iPhone in Q323 same with 5nm H2 19 production we got iphone in Q320 with N5 so do you think this time will be different ?

The timing of the comment matters though, if it was before 18a was downgraded, then the comment may no longer apply.

This matters but i don't remember the exact level of downgrade iirc 20A was 10-15% better than I3 and 18A was 5-10% better than 20A and we got 18A 15% better than I3

 

[Hitman928]

You know from historical trends that Apple gets a year of exclusivity from new TSMC Process not iterations So N3B entered in HVM in H2 22 we got it in iPhone in Q323 same with 5nm H2 19 production we got iphone in Q320 with N5 so do you think this time will be different ?

There are rumors that Apple won’t be the first N2 customer but I don’t really care, I was just pointing out when N2 hits HVM. Whether AMD gets a crack at it then is a different discussion point.

This matters but i don't remember the exact level of downgrade iirc 20A was 10-15% better than I3 and 18A was 5-10% better than 20A and we got 18A 15% better than I3

Yes, it dropped from 26.5% improvement over I3 to 15%, at least in PPW. That would be enough to drop the comparison from N3P to N3E.

 

[511]

There are rumors that Apple won’t be the first N2 customer but I don’t really care, I was just pointing out when N2 hits HVM. Whether AMD gets a crack at it then is a different discussion point.

Those will be rumours cause apple gets the first wafer out of every new node that is guaranteed for last few years

Yes, it dropped from 26.5% improvement over I3 to 15%, at least in PPW. That would be enough to drop the comparison from N3P to N3E.

N3P -> N3E is just 5% difference according to TSMC
Those estimates were 2022 and TSMC commented in 24 and intel published details last quarter to Public inside the ecosystem everyone has the info.we still have IEDM in December we will know by than but those are within estimates(15.5-26.5%)

Intel, TSMC to detail 2nm processes at IEDM

Intel's attempts to get back to the leading-edge in chipmaking and foundry TSMC's steps defining that leading-edge will be on show at this year's International Electron Devices Meeting (IEDM) coming up in December, in San Francisco.

www.eenewseurope.com

 

[oak8292]

Those will be rumours cause apple gets the first wafer out of every new node that is guaranteed for last few years

N3P -> N3E is just 5% difference according to TSMC
Those estimates were 2022 and TSMC commented in 24 and intel published details last quarter to Public inside the ecosystem everyone has the info.we still have IEDM in December we will know by than but those are within estimates(15.5-26.5%)

Intel, TSMC to detail 2nm processes at IEDM

Intel's attempts to get back to the leading-edge in chipmaking and foundry TSMC's steps defining that leading-edge will be on show at this year's International Electron Devices Meeting (IEDM) coming up in December, in San Francisco.

www.eenewseurope.com

Actually, Huawei was the lead customer on N5 but that was just before they lost access to production at TSMC. Huawei had become a member of the 10%+ revenue club with Apple at TSMC. TSMC briefly cancelled some EUV orders when Huawei was put on the blacklist. This was back in pandemic days and TSMC quickly reordered the EUV when demand went through the roof.

“Kirin 9000 chipset which is manufactured on a new 5nm manufacturing node,”

AnandTech Forums: Technology, Hardware, Software, and Deals

Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.

www.anandtech.com

If Nvidia has placed a large enough order they maybe able to ‘co-produce’ with Apple. However, it seems unlikely based on the size of their die but they may be a really fast follow on Apple. Nvidia has now joined Apple in the 10%+ revenue club.

Analyst estimates Nvidia is now TSMC's second largest customer accounting for 11% of revenue in 2023

Nvidia paid TSMC $7.73 billion in 2023 for its services

www.tomshardware.com

 

[SiliconFly]

.

 

[OneEng2]

I thought it was 30% from the benches done by David Huang.I wasn't talking about AVX-512 Performance cause Skymont will loose there Also 2nm GAA is not shipping before Q4 2026 . Intel has 1 year and than after 9 months if Zen6 we have Arctic wolf with 512C/T rouge river forest 🙂 in 2027

N2 is H2 2025. N2P H2 2026. Based on Zen6 roadmaps and TSMC roadmaps and information on Zen 6 showing which nodes it is planned to be produced on, I put the info together in a single speculation of 32 core CCD's of Zen 6 on N2 not too long after Q4 2025 making the Zen 6 part the competition to Clearwater vs current Turin.

 

[OneEng2]

CWF with 288 Darkmont cores should mop the floor with AMD's server product line.


With 288 powerful Darkmont cores, CWF will be the undisputed leader next year.


A theoretical AMD Zen 6 384C/768T part is not scheduled for 2025, probably 2026 (if it exists). Assuming it does exists, then it may be facing of a theoretical 576C/576T Intel server part based on Arctic Wolf cores. AMD wouldn't stand a chance.

CWF isn't going to be released until late 2025. The replacement will not be out until 2027. Still, Intel is going to have to come up with more than a 288 core DC part if they want to compete with Zen 6 in 2026. Furthermore, they better be bringing back SMT if they wish to have any hope of hanging with Zen in DC IMO.

I think that we will get much clarity as CWF design takes shape. It is my understanding that the CWF replacement will be on 14A .... which makes sense as it will be competing with N2P in 2027.

... so Intel's server future parts success is largely reliant on Intel's process roadmap being executed IMO.

Though I could be mistaken.

 

[Doug S]

Those will be rumours cause apple gets the first wafer out of every new node that is guaranteed for last few years

Apple has to have something to put the chips in. If N2 comes too late for A19/M5, what would they do with that first wafer?

Now, I'm still of the opinion that given the N2 timeline, in particular having reached the 80% threshold for risk production in late May, that N2 may reach mass production before H2. Or even if it doesn't "officially" start mass production until H2, that they might be producing enough wafers for Apple to do A19P and M5 on it. Apple would have to accept some risk of slightly less than mass production quality yields if they take early wafers, but I think they'd be fine with that since they'd only be looking at a few percent points of difference.

Not saying that will happen, just that's the way I'd bet knowing what we know now.

But like I said, if Apple does not use N2 for A19/M5, and it is delivered in H2 (almost certainly Q3 based on the above) then Apple isn't going to have much for it. I suppose they could delay M5 a bit to wait for it, but Apple Silicon volume is much smaller than iPhone volume so other customers would be able to get wafers a lot sooner than if they are also competing with A19P.

 

[DavidC1]

I also found this interesting. We've seen other reviewers report on the high memory latency for the p-cores, but I haven't seen memory latency numbers for the e-cores. 194 ns is so high that I wonder if they're doing something wrong with the testing. If it's accurate then it makes the e-cores that much more impressive.

So the memory system hobbled Skymont is 21% faster per clock in Int and 42% faster in FP compared to Raptormont. Not seeing 30% in Int may just be due to this. The FP is likely even more crippled because it has higher bandwidth requirements.

The Lion Cove P core with 3x the core size is 7.7% faster in Int and 3.2% faster in FP per clock compared to Skymont. So there's a direct possibility that Darkmont might be entirely Lion Cove class.

 

[DavidC1]

@GTracing What the heck?

Geekerwan overclocked the following:
-NGU from 2.6GHz to 3.2GHz
-D2D from 2.1GHz to 3.5GHz
-Ring from 3.8GHz to 4.2GHz

The E core latency went down from 194.2ns to 113ns or a 72% difference. D2D OC is 67%, so a slow D2D may be responsible for the super high latency. I would have liked him to test perf/clock after the overclocks.

 

[cannedlake240]

replacement will not be out until 2027

Word is it's(Rouge river Forest) canned to redirect resource to AI or for plain cost cutting... So 192C? Diamond Rapids and it's successor, Coral Rapids was it, may be all they have against AMD until 2028-30, when the E core is planned to make a debut. Pats remarks about reducing server CPU roadmap complexity seemingly reflect that too

 

[DavidC1]

That is expected, the advantage that Raptor had, wider registers, was taken away, with those compiler settings. For int it is less relevant as x264 will be the only subtest to benefit, but from FP point of view it's a different story.

Arrowlake has a super slow D2D, which is likely a big reason why it has super high memory latency. Geekerwan overclocked D2D by 67%, NGU by 23%, and Cache by 10.5% which lowered the latency to 110ns from 194ns.

While a different compiler setting might have made Raptorlake faster, a fixed fabric would also make Skymont faster.

@SiliconFly I doubt core counts are going to be that high. Process gains are really slowing down, and they'll need to spend whatever they get on a new uarch. No room for more cores, plus you run into scaling issues.

 

[cannedlake240]

You're ignoring clock rates
Considerable disappointment follows those extrapolating from only IPC.

Skymont doesn't regress clocks on desktop, and can be overclocked to 5Ghz. Even if 18A is overall worse than N3B(which isn't a given), the core should still clock way above the paltry 3Ghz of SRF. Using smaller 18A tiles is also a plus for perf on CLF

 

[DavidC1]

Skymont doesn't regress clocks on desktop, and can be overclocked to 5Ghz. Even if 18A is overall worse than N3B(which isn't a given), the core should still clock way above the paltry 3Ghz of SRF. Using smaller 18A tiles is also a plus for perf on CLF

The ultimate performance depends on if they get everything right, and uncore performance is even more important on a server CPU with many cores.

Granite Rapids goes from being 20% difference in 1P to 40% difference in 2P, because it doesn't scale well. Clearly, they need to fix this, but the reality is the difference exists.

Since CWF has 288 cores I doubt clock higher. It seems Sierra and Zen 4c clocked roughly similar so the differences are going to be elsewhere, like clocks, fabric, and platform.

CWF is also on the Birch Stream platform, meaning socket upgradable. The problem is if Birch Stream has a scaling issue, CWF will inherit this to a degree.

 

[cannedlake240]

The ultimate performance depends on if they get everything right, and uncore performance is even more important on a server CPU with many cores.

Granite Rapids goes from being 20% difference in 1P to 40% difference in 2P, because it doesn't scale well. Clearly, they need to fix this, but the reality is the difference exists.

Since CWF has 288 cores I doubt clock higher. It seems Sierra and Zen 4c clocked roughly similar so the differences are going to be elsewhere, like clocks, fabric, and platform.

Wasn't it suggested in one of the uarch deep dives that the 3 cycle L1 was traded for more speed? Also CLF supposedly has over 2x amount of LLC found on SRF, so over 432mb on base tiles...

 

[DavidC1]

Mobile vs Desktop differences are real.
Arrowlake's cores are still faster per clock than Lunarlake's cores.

Lion Cove is 7% faster on Arrowlake than on Lunarlake. Skymont on Arrowlake is almost 26% faster per clock over Skymont on Lunarlake.

14900K's E cores are 14% faster than Crestmont(a faster core) on Meteorlake.

Wasn't it suggested in one of the uarch deep dives that the 3 cycle L1 was traded for more speed? Also CLF supposedly has over 2x amount of the LLC found on SRF, so over 432mb on base tiles...

Yes, but that's for Desktops. They'll be thermally limited with 288 cores.

 

[SiliconFly]

.

 

[Meteor Late]

Mobile vs Desktop differences are real.
Arrowlake's cores are still faster per clock than Lunarlake's cores.

Lion Cove is 7% faster on Arrowlake than on Lunarlake. Skymont on Arrowlake is almost 26% faster per clock over Skymont on Lunarlake.

14900K's E cores are 14% faster than Crestmont(a faster core) on Meteorlake.

Yes, but that's for Desktops. They'll be thermally limited with 288 cores.

LPDDR vs DDR is one of the main differences? what else?

 

[DavidC1]

Area-wise, Skymont is competitive to Oryon-M. While Skymont seems much wider, it's 0.9mm2 for Oryon-M vs 1.15mm2 for Skymont, meaning the additions to Skymont isn't big as the high level specs suggest.

Also, consider the 1.78 for SpecInt is Skymont in Arrowlake. I think Oryon-M is around that level. So if you assume Skymont is 10% faster, then it's even better for Skymont. Considering it's an x86 core, it's pretty damn good. I think the E core team can also do a better job.

LPDDR vs DDR is one of the main differences? what else?

Power management. It has many more steps, and it's more aggressive, and slower to get out of. This is the biggest reason. Everything is like that, from the CPU cores, to the memory, to IO such as SSD, keyboard, webcam, etc.

 

[511]

Actually, Huawei was the lead customer on N5 but that was just before they lost access to production at TSMC. Huawei had become a member of the 10%+ revenue club with Apple at TSMC. TSMC briefly cancelled some EUV orders when Huawei was put on the blacklist. This was back in pandemic days and TSMC quickly reordered the EUV when demand went through the roof.

“Kirin 9000 chipset which is manufactured on a new 5nm manufacturing node,”

AnandTech Forums: Technology, Hardware, Software, and Deals

Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.

www.anandtech.com

If Nvidia has placed a large enough order they maybe able to ‘co-produce’ with Apple. However, it seems unlikely based on the size of their die but they may be a really fast follow on Apple. Nvidia has now joined Apple in the 10%+ revenue club.

Analyst estimates Nvidia is now TSMC's second largest customer accounting for 11% of revenue in 2023

Nvidia paid TSMC $7.73 billion in 2023 for its services

www.tomshardware.com

Intel is also part of 10% club for now 🙂.I forgot Huawei but that is not coming back

Apple has to have something to put the chips in. If N2 comes too late for A19/M5, what would they do with that first wafer?

Now, I'm still of the opinion that given the N2 timeline, in particular having reached the 80% threshold for risk production in late May, that N2 may reach mass production before H2. Or even if it doesn't "officially" start mass production until H2, that they might be producing enough wafers for Apple to do A19P and M5 on it. Apple would have to accept some risk of slightly less than mass production quality yields if they take early wafers, but I think they'd be fine with that since they'd only be looking at a few percent points of difference.

Not saying that will happen, just that's the way I'd bet knowing what we know now.

But like I said, if Apple does not use N2 for A19/M5, and it is delivered in H2 (almost certainly Q3 based on the above) then Apple isn't going to have much for it. I suppose they could delay M5 a bit to wait for it, but Apple Silicon volume is much smaller than iPhone volume so other customers would be able to get wafers a lot sooner than if they are also competing with A19P.

M5 is N3P from the rumours there is no way for N2 products before H2 2026 and AMD doesn't lead exactly like Apple so Zen6C is not happening before Q426

 

[511]

Word is it's(Rouge river Forest) canned to redirect resource to AI or for plain cost cutting... So 192C? Diamond Rapids and it's successor, Coral Rapids was it, may be all they have against AMD until 2028-30, when the E core is planned to make a debut. Pats remarks about reducing server CPU roadmap complexity seemingly reflect that too

Rouge river is not canned considering its the P core team that is axed and the complexity were the different platforms they had Xeon 6 6700/6900 series which will be unified into single platform

 

[Doug S]

Intel is also part of 10% club for now 🙂.I forgot Huawei but that is not coming back

M5 is N3P from the rumours there is no way for N2 products before H2 2026 and AMD doesn't lead exactly like Apple so Zen6C is not happening before Q426

N2 enters mass production in H2 2025. And unlike N3B/N3E which entered risk production in December making their "H2" start of mass production the following December, N2 entered risk production the first week of July - and qualified for it yield wise in late May.

So while it is certainly possible M5 is N3P, the idea that there will be no N2 products before H2 2026 is completely false, unless TSMC totally drops the ball on N2 which has by all indications been going well if not exceeding their timetable.

 

[511]

N2 enters mass production in H2 2025. And unlike N3B/N3E which entered risk production in December making their "H2" start of mass production the following December, N2 entered risk production the first week of July - and qualified for it yield wise in late May.

So while it is certainly possible M5 is N3P, the idea that there will be no N2 products before H2 2026 is completely false, unless TSMC totally drops the ball on N2 which has by all indications been going well if not exceeding their timetable.

I am talking about products in hands of consumer like us or the server guys do you think there is a chance that we will have new N2 product in our hand by May/June considering the fact that it is a New node family not iteration like N3E and N3P

 

[511]

TSMC N2 mass production is 2026

https://twitter.com/x/status/1853608843235725622

https://twitter.com/x/status/1853612313863205138

Also found this graph

 

[DrMrLordX]

CWF isn't going to be released until late 2025.

That seems a bit late to market if they expect to compete with Turin dense.