Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[cannedlake240]

Yeah, they'll just ask IFS to give them a better deal.

Well the rumormill suggests it's the high end skus being ourosourced...

 

[Joe NYC]

Clearwater forest will do hybrid bonding with SRAM and Imc On Base Tile

Clearwater Forest seems like Intel finally going to get one right.

Making V-Cache optional, meaning that the CPU can work with or without is - that is no doubt more of a challenge to achieve, and maybe Intel just does not want to risk it.

But who knows where AMD will be with Zen 6 in 2 years against NVL. There may be a 3rd generation of V-Cache Intel will have to compete against, and AMD has kept cost efficiency as a high priority.

And the cost delta between the advanced node and SRAM node has only grown.

At the start, AMD used the same node, but SRAM uses fewer metal layers, so the die area was cheaper than what die area costs of a CPU die. And smaller overall CPU die improves yields

By 2026, there will be at least 2 node gap between SRAM die and advanced node for compute. So AMD can include V-Cache in wider range of CPUs, including mainstream, while (as the Twitter poster suggested), for Intel it may be limited to their KS SKU.

 

[511]

Well the rumormill suggests it's the high end skus being ourosourced...

I have heard inverse the main compute seems to be at intel supporting chip let's are outsourced

 

[coercitiv]

Really so they can just increase the L3 by 4x without it incurring a massive latency penalty? Vcache is 4-5 cycle for instance

Of course it incurs a latency penalty, there's no free lunch. At best you move the latency burden from cache to ring. No matter how you slice it (pun intended) it's still a system that pays a latency cost as it grows in size.

Well the rumormill suggests it's the high end skus being ourosourced...

My reply implied that the product needs to stand on it's own feet, it needs to be fully viable commercially whether manufactured at TSMC or internally. IFS needs all the margin they can get.

 

[naukkis]

Really so they can just increase the L3 by 4x without it incurring a massive latency penalty? Vcache is 4-5 cycle for instance

They are using 12MB L2 slices on other cpu designs with about 15-20 cycle latency @4ghz speeds. 4MB slice is at best something like 3-5 clock cycles faster. L3 latency on 12-stop Intel ring is something like 60-80 cycles @4ghz. So when they triple L3 slice L3 latency might increase 5-10% but that's not problem at all.

 

[alcoholbob]

This is all nice and interesting, but since NVL isn't planned until late 2026 or early 2027, this could be just another halo product that ends up getting cancelled if Intel's financials don't get better.

 

[DavidC1]

Really so they can just increase the L3 by 4x without it incurring a massive latency penalty? Vcache is 4-5 cycle for instance

The latency increase might not be that big, and it'll depend more on how well designed the fabric is, however...

I'm still thinking they'll introduce new tech for the big L3 cache version. They've been talking about it for over a decade now, and it's kinda overdue.

Even if there is a latency increase, as long as it's significantly lower than main memory it'll benefit from the workload not having to go out to higher latency, lower bandwidth RAM. They got quite a bit from eDRAM and it was slower than L3.

Clearwater forest will do hybrid bonding with SRAM and Imc On Base Tile

Does it have the memory controller? The Intel page about it doesn't say anything specific. It'll certainly be used to communicate between the dies though.

 

[adroc_thurston]

Does it have the memory controller?

Yeah, all Intel mesh parts have an IMC stop somewhere.

 

[511]

Does it have the memory controller? The Intel page about it doesn't say anything specific. It'll certainly be used to communicate between the dies though.

Yes the white paper said it

https://www.intel.com/content/dam/www/central-libraries/us/en/documents/2024-02/intel-tech-clearwater-wp.pdf

 

[Joe NYC]

I'm still thinking they'll introduce new tech for the big L3 cache version. They've been talking about it for over a decade now, and it's kinda overdue.

I just went through the transcript of Intel conference call, and in that call, Intel said that some of the Nova Lake CPUs will be TSMC only.

It is a safe assumption that it will be the highest end SKU that will have TSMC compute die, so maybe Intel is planning on putting this 144 MB of SRAM on TSMC N2 or N3...

 

[511]

Yeah, all Intel mesh parts have an IMC stop somewhere.

Having on mesh on the same die is one thing but having on different die on Hybrid Bonding is first for Intel

 

[Joe NYC]

Yeah, all Intel mesh parts have an IMC stop somewhere.

What is your assessment of that? It looks like Intel has started doing it with Sierra Forrest, including 4 memory channels on compute dies, and then, including 2 or 3 of these dies in the package.

And then, the IO chiplets seem separate, not including memory controllers.

It is a different arrangement, from what AMD has been doing since Rome. It seems like it is not a bad idea...

 

[511]

I just went through the transcript of Intel conference call, and in that call, Intel said that some of the Nova Lake CPUs will be TSMC only.

It is a safe assumption that it will be the highest end SKU that will have TSMC compute die, so maybe Intel is planning on putting this 144 MB of SRAM on TSMC N2 or N3...

Nope you got the earnings wrong

https://twitter.com/x/status/1852109852492935265

 

[Joe NYC]

Nope you got the earnings wrong

https://twitter.com/x/status/1852109852492935265

No, that's just Gelsinger being evasive, deliberately wording his answer in imprecise way, in order to allow the reader read his wishful thinking into the answer.

I think the translation of the quote is that Intel is going to use Intel's own 18A for all of Panther Lake, but some SKUs of Nova Lake will be TSMC.

And these TSMC only SKUs will be the high end ones, from the context of the theme of the margin discussion of the entire call.

Which would be consistent with "large majority" comment. For example, between 8+16 and 6+8 dies, large majority of product sold is the low end 6+8 die.

 

[511]

No, that's just Gelsinger being evasive, deliberately wording his answer in imprecise way, in order to allow the reader read his wishful thinking into the answer.

I think the translation of the quote is that Intel is going to use Intel's own 18A for all of Panther Lake, but some SKUs of Nova Lake will be TSMC.

And these TSMC only SKUs will be the high end ones, from the context of the theme of the margin discussion of the entire call.

Which would be consistent with "large majority" comment. For example, between 8+16 and 6+8 dies, large majority of product sold is the low end 6+8 die.

View attachment 110890

Maybe only Halo like U9 but supporting chiplet can be Intel but it will not be a LNL/ARL Scenario of fully TSMC which is a one time thing maybe they are hybrid bonding Intel/Tsmc Silicon Intel is the only company that has done so

 

[LightningZ71]

Given the limitations of the ring bus speed on Arrow Lake, it does make sense to sacrifice a few cycles of latency on the L3 to triple or more it's size to keep as many accesses as possible off of the ring bus for many multiples of that same latency, and to sharply reduce IMC accesses outside of that bus. It's going to cost them dearly on silicone, and, unless they waste a lot of floorplan space for the base product, will probably require a unique tile arrangement, further increasing development costs.

 

[fastandfurious6]

Yeah it looks like intel "18A" still won't have high-end SKUs

It's been a pattern right? Intel has an issue with producing high-end SKUs on its own process

Basically Alder Lake saved the company..... the only proper high-end chip for many years. although with major warts i.e. corrosion and 500watts juicing lol

but that was 2021. Intel needs a new Alder Lake to save itself again!

 

[511]

Yeah it looks like intel "18A" still won't have high-end SKUs

LoL if you are counting CLW-F/PTL/NVL/DMR isn't that enough also they are looking to diversify with Chiplets it is about volume and cost more than High end SKU High End SKU have the highest Margins while mid end have low

It's been a pattern right? Intel has an issue with producing high-end SKUs on its own process

Basically Alder Lake saved the company..... the only proper high-end chip for many years. although with major warts i.e. corrosion and 500watts juicing lol

but that was 2021. Intel needs a new Alder Lake to save itself again!

You are just confusing Design and Fabs there is nothing that have shown Fabs being broken now time and time again it's been design for past year

 

[511]

Also we don't know chiplet strategy with 18A
ARL/MTL Design was a bit flawed LNL Corrected it and PTL/NVL Improves upon it

 

[SiliconFly]

.

 

[fastandfurious6]

No Money = No Honey

No High End Chip = No Honey

it's simple really

 

[511]

No Money = No Honey

No High End Chip = No Honey

it's simple really

Is it though you need a good product not a high end product look at 4060/4070 lol it is not high end but Nvidia still makes nice money of it they have their own fabs so they have to look for utilisation and 3rd party volume also

 

[SteinFG]

Does panther lake have laptop dGPU designs? or is it just arrow lake for two years there? Cause the latest rumor is that top panther lake die will be 4P+8E+4LPE like 12600H or smth

 

[trivik12]

They should have killed p cores with Arctic wolf itself taking care of everything. Reduce complexities and even go back to monolithic for laptop soc.

 

[adroc_thurston]

and even go back to monolithic for laptop soc.

But they did, LNL is monolithic.