Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

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Tigerick

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Apr 1, 2022
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Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

Intel Alder Lake - NIntel Wildcat LakeIntel Lunar LakeMediatek D9500
Launch DateQ1-2023Q2-2026 ?Q3-2024Q3-2025
ModelIntel N300?Core Ultra 7 268VDimensity 9500 5G
Dies2221
NodeIntel 7 + ?Intel 18-A + TSMC N6TSMC N3B + N6TSMC N3P
CPU8 E-cores2 P-core + 4 LP E-cores4 P-core + 4 LP E-coresC1 1+3+4
Threads8688
Max Clock3.8 GHz?5 GHz
L3 Cache6 MB?12 MB
TDP7 WFanless ?17 WFanless
Memory64-bit LPDDR5-480064-bit LPDDR5-6800 ?128-bit LPDDR5X-853364-bit LPDDR5X-10667
Size16 GB?32 GB24 GB ?
Bandwidth~ 55 GB/s136 GB/s85.6 GB/s
GPUUHD GraphicsArc 140VG1 Ultra
EU / Xe32 EU2 Xe8 Xe12
Max Clock1.25 GHz2 GHz
NPUNA18 TOPS48 TOPS100 TOPS ?






PPT1.jpg
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As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



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mikk

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May 15, 2012
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The E core is set to replace the P core very soon (probably 2026 or 2027).

No chance. 2026-2027 is Nova Lake coming with a P+E architecture. Then I would expect a refresh from this a year later. Earliest for something new would be a 2028-2029 timeframe.
 

Abwx

Lifer
Apr 2, 2011
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Oh pls. Zen 5 is equal cr@p like ARL this gen. Thats why everyone calls it Zen 5%. And seeing the range of Core Ultra 200 series processors, I'm sure ARL will outsell Zen 5 by a wide margin as usual.

I dont pay attention to WCCF troll members sayings, i look at the numbers, so far the 9950X is 10% faster than both 7950X and 14900K in MT at a lower power, and according to Intel themselves is faster in GB ST than the 285K, GB is certainly not the best ST metric but at least it include both INT and FP in its average.

For this gen it s the clear winner, and that s with a half node deficit, Intel are lucky that N3 has 15-18% better per/Watt than N4P, otherwise their 250W chip would had faced a 150W one at comparable perfs.

Clearly the lack of SMT is a disastrous move as it would had allowed the same perfs at 20% lower power, but according to Computerbase reviewer Intel likely removed it because their implemetation wasnt satisfying, and personaly i think that they were also too confident on their node advantage.
 

Hulk

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Oct 9, 1999
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Honestly, if the densely packed E-cores can already reach up to 4.9 GHz, I struggle to see the reason for classic P cores for most future client SKUs (unless Cougar Cove is a much bigger bump in IPC than Lion Cove).

I'm pretty sure, that it would be possible to make "performance versions" of the Skymont successor, that would have more cache and be higher clocked (low 5Ghz range), trading a bit of area for clock speed, sorta the reverse of Zen 5c.

It doesn't make that much sense still in the context of Lion Cove vs Skymont, but if Intel can continue to deliver decent E-core IPC bumps in the future, it might already make sense with the next gen E-core.
I think we are looking at the P core to E core ratio decreasing as the E's catch the P's. Perhaps 6+20, then 4+24.
 
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Hitman928

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Cinebench R23 MT: 42286
Cinebench 2024 MT: 2355


Hmm, not really a good result. I knew ST was going to be tough for ARL to improve much over RPL, but these results show no improvement in MT either. I’m sure you still get better efficiency at lower power levels, but not enough to take the lead against the competition. I expect much better results on mobile, but desktop results so far seem really disappointing.
 

AcrosTinus

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Jun 23, 2024
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I think we are looking at the P core to E core ratio decreasing at the E's catch the P's. Perhaps 6+20, then 4+24.
Currently Raptor Lake even at an IPC disadvantage can get more done on the P-Cores due to HT. Hence we need more P-Cores not less.

The Best setup was 8P+8E the next best one would be 10P+8E or 10P+16E.
 
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Hitman928

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Apr 15, 2012
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I wonder how much difference ARL will have at different Power Levels

I expect it will be similar to Zen 4 where ARL wins at lower power levels but scales much worse at higher power levels. I’m guessing a little less than 250W is where things really start to flip and as you push higher than that, RPL catches up quickly.
 

GTracing

Senior member
Aug 6, 2021
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Yea except:

macroop.jpg

The E cores are a totally different path from the P core lineup, and the divergence starts all the way back to the original Pentium.

@poke01 Hulk, he probably means architecturally because we aren't gonna get much higher than 6GHz.
Skymont doesn't have a uop cache, but it does still decode instructions into micro ops like P6.

Decoders feed micro-ops into queues in front of the renamer, which help absorb short duration delays. Besides a 3-wide decoder, a frontend cluster includes its own micro-op queue. Copy-pasting the cluster again brings micro-op queue capacity from 2×32 = 64 on Crestmont to 3×32 = 96 entries in Skymont. It’s nowhere near the 192 entry micro-op queue capacity on Lion Cove, but it does get close to some older cores. For reference, Zen 4 has a 144 entry micro-op queue.

Sandy bridge was the first intel CPU with a micro op cache.

Anybody know who came up with micro-ops and when? Saved x86 I would think?
The Pentium Pro (P6) was the first to have the idea of micro-ops. But every x86 CPU since the 8086 has broken instructions down into some form of internal representation before they're executed.

1951, Maurice Wilkes came up with the idea of microcode: instead of building the control circuitry from complex logic gates, the control logic could be replaced with another layer of code (i. e. microcode) stored in a special memory called a control store. To execute a machine instruction, the computer internally executes several simpler micro-instructions, specified by the microcode. In other words, microcode forms another layer between the machine instructions and the hardware.

The fact that x86 instructions have to be broken up into micro-ops isn't an accident or workaround. It was an intentional design decision.
 

Josh128

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Oct 14, 2022
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Hmm, not really a good result. I knew ST was going to be tough for ARL to improve much over RPL, but these results show no improvement in MT either. I’m sure you still get better efficiency at lower power levels, but not enough to take the lead against the competition. I expect much better results on mobile, but desktop results so far seem really disappointing.

What is up with the 328W on that R23 MT run? Is that CPU or entire system? If its just the CPU that is a horrendous result indeed.
 

Hitman928

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What is up with the 328W on that R23 MT run? Is that CPU or entire system? If its just the CPU that is a horrendous result indeed.

It’s CPU (package) only. I’m guessing someone ran with PL2=PL1 unlimited and this was the result. Probably very little, if any, gain over stock but power goes up regardless. You would need to do manual tweaking to improve the score. Basically how Zen 4 is.
 
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Tup3x

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At this point one can only hope that at least idle/light usage is low power. Not looking too good at the moment but who knows, maybe some models are pretty good for mixed usage.

Anything over 175W (when using default settings) is instant failure in my opinion though.
 
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Abwx

Lifer
Apr 2, 2011
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Thats a really horrible perf/consump ratio

My tweaked 9950X, scores higher than that @230W

View attachment 109880
One has to wonder how they forged the curve below, although they will do better in CB2024 as it s their usual trick, to get Maxon, with wich they have a contract since CB 11.5, releasing a new and well doctored version of CB just before a new CPU is launched, they used this trick with CB R20/R23 released just in time to give an hedge to ADL in respect of Zen 3.

15-1080.d9e4114e.png


 

poke01

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Mar 8, 2022
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One has to wonder how they forged the curve below, although they will do better in CB2024 as it s their usual trick, to get Maxon, with wich they have a contract since CB 11.5, releasing a new and well doctored version of CB just before a new CPU is launched, they used this trick with CB R20/R23 released just in time to give an hedge to ADL in respect of Zen 3.

15-1080.d9e4114e.png


It’s best to leave out conspiracy theories especially when the 9950X is better in CB2024 in MT and scores 2305 at 200watts.

While Intel requires 279 watts to score 2355. You also have keep in mind CB2024 was developed in collaboration with multiple vendors. Especially since it’s the first Cinebench with proper ARM support and the render has changed from Pro Render to Redshift.





 

poke01

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Mar 8, 2022
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If people have noticed by now that CB2024 chart by Intel marketing isn’t true.
 

The Hardcard

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Oct 19, 2021
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One has to wonder how they forged the curve below, although they will do better in CB2024 as it s their usual trick, to get Maxon, with wich they have a contract since CB 11.5, releasing a new and well doctored version of CB just before a new CPU is launched, they used this trick with CB R20/R23 released just in time to give an hedge to ADL in respect of Zen 3.

15-1080.d9e4114e.png


Could you define your use of the term “doctored?” What trick is happening?