Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[Joe NYC]

Intel likely secured this 3nm quite early, possibly before AMD decided that they were not going to use 4nm. In the time that AMD decided they were going to stick with 4nm from Zen 4 to Zen 5, pricing renegotiation would have had to take place. Huang was probably already producing boatloads of Ada and Hopper GPUs and AMD was producing MI-300X and EPYC, most of which are more profitable per mm2 than client CPU. Im not saying the 4nm is more expensive than the 3, Im saying its very close or on par-- and even if its not, it still has pricing pressure because AMD can repurpose the same die not selling on desktop to be use in EPYC, which commands a higher price. All of this adds up to Zen 5 being expensive. AMD has no incentive to lower the price, its better for them to just be content with selling the silicon in other products.

We'll see who is right very soon. I'd be willing to bet that Arrow Lake will not be any more expensive than launch pricing of Zen 5, and could actually have cheaper launch pricing, which would validate my line of thinking here.

Your guess was pretty good, based on Raichu prices.

 

[511]

TSMC N3B is very expensive for Intel. They commented on it multiple times in their latest earnings call. It is one of the key factors they identified for low gross margin forecasts for the end of the year and into 2025.

N3B for whole die like LNL is expensive yes but not ARL as a whole in which a part is N3B rest is taken by SOC

 

[511]

ARROW LAKE n3b 8+16 die size is approx 13.69X6.45 approx 88.30 mm2




A 19K WAFER AND 572 U9 Dies it is approx 33 USD for the CPU die it is an approximation not counting defective can be U7 i took yield as 0.15 cause iirc N3B yield are behind N5 which is <0.1 so i took it 1.5

 

[Hitman928]

N3B for whole die like LNL is expensive yes but not ARL as a whole in which a part is N3B rest is taken by SOC

Are you saying N3B is less expensive than prior nodes if the die is smaller? It’s expensive either way. Obviously less die space on the most expensive node is better, but it’s still just as expensive a node, is the biggest part of the SOC (at least for the high end), and you have to deal with the additional advanced packaging costs, including a bigger base tile. There's a reason Intel said that margins will remain low until they can get off of external nodes and transition to 18a.

 

[511]

Are you saying N3B is less expensive than prior nodes if the die is smaller? It’s expensive either way. Obviously less die space on the most expensive node is better, but it’s still just as expensive a node, is the biggest part of the SOC (at least for the high end), and you have to deal with the additional advanced packaging costs, including a bigger base tile. There's a reason Intel said that margins will remain low until they can get off of external nodes and transition to 18a.

Nope i am saying the total cost for the entire chip will be the deciding factor based on my copy+paste skills i have shown above it costs around $33 to produce the CPU Die

 

[Joe NYC]

What's more expensive: monolithic 260mm2 on Intel 7 or 100mm2 N3 and N6 + foveros and a tiny N5 gfx tile? The difference might not be that much tbh, N3 CPU tile yields must be way higher, they get more i9s and i7s per wafer

That's a complicated question. Under the latest separation of Intel foundry, Intel Foundry charges Intel products like $20 and says the Foundry has a loss of $60 on that sale.

But if it was 260 mm2 N7 vs: combined costs of

100 mm2 N3N
44 mm2 N5
100 mm2 N6
27 mm2 N6
Foveros die + packaging

Arrow Lake is still definitely more expensive. Probably +50% to +100% the cost vs. what equivalent 260 mm2 N7 would cost.

 

[cannedlake240]

44 mm2 N5

It's way smaller, around 24mm2 and likely reused from MTL-U

 

[Joe NYC]

It's way smaller, around 24mm2 and likely reused from MTL-U

Which one is smaller? I listed die sizes of 3 non-compute tiles from Meteor Lake.

 

[cannedlake240]

Which one is smaller? I listed die sizes of 3 non-compute tiles from Meteor Lake.

64EU Graphics. MTL-H uses 128EU gfx

 

[511]

That's a complicated question. Under the latest separation of Intel foundry, Intel Foundry charges Intel products like $20 and says the Foundry has a loss of $60 on that sale.

But if it was 260 mm2 N7 vs: combined costs of

100 mm2 N3N
44 mm2 N5
100 mm2 N6
27 mm2 N6
Foveros die + packaging

It is 23mm2 for the gpu it is already in MTL-U IO is around 20 iirc N3B is 90mm2 and SOC 100 yes

Arrow Lake is still definitely more expensive. Probably +50% to +100% the cost vs. what equivalent 260 mm2 N7 would cost.

Yes no doubt it is more expensive than RPL

 

[511]

Which one is smaller? I listed die sizes of 3 non-compute tiles from Meteor Lake.

From MTL U

 

[Joe NYC]

64EU Graphics. MTL-H uses 128EU gfx

I see. Good catch.

 

[Hitman928]

ARROW LAKE n3b 8+16 die size is approx 13.69X6.45 approx 88.30 mm2

View attachment 109010

View attachment 109012
A 19K WAFER AND 572 U9 Dies it is approx 33 USD for the CPU die it is an approximation not counting defective can be U7 i took yield as 0.15 cause iirc N3B yield are behind N5 which is <0.1 so i took it 1.5

I expect the 8+16 die to be larger than that. I also think you are discounting the cost of N3B wafers. Either way, the point is that N3B is expensive, advanced packaging is expensive, and there is no way that Intel is getting a better deal with N3B + N4/N5/N6 on advanced packaging than AMD is for N4P + N6 with much cheaper packaging and is obviously more expensive than if they had gone with N4P themselves.

 

[511]

I expect the 8+16 die to be larger than that. I also think you are discounting the cost of N3B wafers.

Nope it was always rumored to be 19k-20k per wafer also why do you expect it to be larger than that never mind found the reason i almost forgot about L2 cache from 2.5 -> 3 so yeah additional few mm2 but i think it will be less than 100

Either way, the point is that N3B is expensive, advanced packaging is expensive, and there is no way that Intel is getting a better deal with N3B + N4/N5/N6 on advanced packaging than AMD is for N4P + N6 with much cheaper packaging and is obviously more expensive than if they had gone with N4P themselves.

Yes i fully agree it is not cheaper than Zen 5 but by how much that is an open question

 

[Hitman928]

Nope it was always rumored to be 19k-20k per wafer also why do you expect it to be larger than that never mind found the reason i almost forgot about L2 cache from 2.5 -> 3 so yeah additional few mm2 but i think it will be less than 100

Yes i fully agree it is not cheaper than Zen 5 but by how much that is an open question

I think right around 100 mm2 but not 100% sure. That price I believe is N3E, not N3B, N3B is noticeably more expensive.

My main point was that there was no way ARL wasn't more expensive, so I'm glad we agree there and I agree that it's difficult to say how much more expensive it is then Zen 5, but it's significant enough for Intel to comment directly on how expensive it is for them to use TSMC with ARL and LNL.

 

[511]

I think right around 100 mm2 but not 100% sure. That price I believe is N3E, not N3B, N3B is noticeably more expensive.

You know that wafer price comes down a bit over time

My main point was that there was no way ARL wasn't more expensive, so I'm glad we agree there and I agree that it's difficult to say how much more expensive it is then Zen 5, but it's significant enough for Intel to comment directly on how expensive it is for them to use TSMC with ARL and LNL.

One thing with Raptor lake is the foundry margin is also going to Intel however they wanna show it in their books if they get nodes competitive to TSMC and similar cost structure their margins are going to improve dramatically

 

[Hitman928]

You know that wafer price comes down a bit over time

View attachment 109014

One thing with Raptor lake is the foundry margin is also going to Intel however they wanna show it in their books if they get nodes competitive to TSMC and similar cost structure their margins are going to improve dramatically

TSMC actually went through multiple price increases over the last few years, though I believe they stabilized and dipped a little in 2023/2024. They are reportedly increasing prices again in 2025.

In 2022, TSMC raised wafer prices by 10%, followed by an additional 5% in 2023. Looking ahead, another 5% blended increase is anticipated for 2025 in a bid to help TSMC's gross margin rebound to 53% - 54% by 2025.

TSMC may increase wafer pricing by 10% for 2025: Report

Chips are getting more expensive.

www.tomshardware.com

Edit: Found the Morgan Stanley analyst's chart showing wafer cost per node changes over time. The chart shows each node with the baseline price being 100% and the percentage point change over 6 years (2025-2026 predicted).

https://twitter.com/x/status/1810368466257662390

 

[511]

TSMC actually went through multiple price increases over the last few years, though I believe they stabilized and dipped a little in 2023/2024. They are reportedly increasing prices again in 2025.

TSMC may increase wafer pricing by 10% for 2025: Report

Chips are getting more expensive.

www.tomshardware.com

Edit: Found the Morgan Stanley analyst's chart showing wafer cost per node changes over time. The chart shows each node with the baseline price being 100% and the percentage point change over 6 years (2025-2026 predicted).

View attachment 109016

https://twitter.com/x/status/1810368466257662390

Could hike and wafer agreement is in advance do you think Intel will pay hiked prices if their agreement already had 19K-20Kfor a fixed amount of wafer after that sure

 

[coercitiv]

wafer agreement is in advance

so why would it matter that wafer prices go down over time then?

 

[511]

so why would it matter that wafer prices go down over time then?

I can negotiate future capacity at discounted price

 

[coercitiv]

I can negotiate future capacity at discounted price

You seem to think price negotiations can only go down. Intel is a direct and vocal competitor, with a widely known need to secure capacity on a leading edge node after multiple manufacturing failures. TSMC may be open for business with everyone, but I doubt they cannot spot a desperate customer when they see one.

 

[gdansk]

You seem to think price negotiations can only go down. Intel is a direct and vocal competitor, with a widely known need to secure capacity on a leading edge node after multiple manufacturing failures. TSMC may be open for business with everyone, but I doubt they cannot spot a desperate customer when they see one.

Intel is a long-time customer of TSMC and on the verge of switching most of their volume to TSMC. I think TSMC will negotiate with them fairly as it weakens a future foundry competitor if even Intel won't use Intel Foundry.

 

[Hitman928]

Could hike and wafer agreement is in advance do you think Intel will pay hiked prices if their agreement already had 19K-20Kfor a fixed amount of wafer after that sure

I'm not going to argue about the exact price as those are under NDA and specific to high volume contracts anyway. The point was that prices haven't come down, they have and are going up.

 

[Hitman928]

Intel is a long-time customer of TSMC and on the verge of switching most of their volume to TSMC. I think TSMC will negotiate with them fairly as it weaken a future foundry competitor if even Intel won't use Intel Foundry.

I'm with @coercitiv on this, Intel is not really in a position to negotiate and TSMC knows it. If Intel signed a long term contract for multiple generations, it would probably be a different story, but Intel has only been talking a lot about getting off of TSMC as quickly as possible. Foundries value not just high volume, but also long term customers. Intel has told the world, they are not a long term customer for TSMC, so TSMC doesn't have much incentive to deal generously with them. I'm sure they're giving them a fair rate, but I doubt it is anything special.

 

[H433x0n]

You seem to think price negotiations can only go down. Intel is a direct and vocal competitor, with a widely known need to secure capacity on a leading edge node after multiple manufacturing failures. TSMC may be open for business with everyone, but I doubt they cannot spot a desperate customer when they see one.

That's not how TSMC works and even if it was It's in TSMC's best interests to treat Intel well. If going with external wafers gives them the best performance and experience, the harder it is for Intel to justify their own fabs.