Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[511]

Let me correct
On October 7 we will get official slides leaked like Lunar lake
On October 10 the official launch will begin

 

[naukkis]

Once you've lost your mind and think a 24 wide design isn't the stupidest thing ever, you better figure out a way to keep it doing something halfway useful when the magic compiler you're depending on fails to materialize (like they always do)

It wasn't traditional 24-way cpu but 4 clustered 6-way cpus with register-to.register moves and ability to execute single thread together. X86 is worst ISA to do such a cpu so Intel would have need to implement new ISA to support that cpu. I speculate that Jim Keller did want to do it with Risc-v ISA and after Intel changed that to x86( and doomed it to fail) he left. Actually rest of Royal core lead designers also left Intel and are building that Royal Core on Risc-V under new startup Ahead computing - curiously see if they can bring something out.

And if they get something good out Intel sure need to reorganize their management layer - sack everybody.

 

[Wolverine2349]

The sample you have is it a QS?

So Arrow Lake can do DDR5 Gear 1??

Shoudl that more than make up for the IMC being on a spearate tile form CPU corers and ring unlike Raptor and Alder? Raptor and Alder can only do DDR5 Gear 2, but they have faster IMC latency due to the IMC being on the same die on CPU cores and ring? Am I right on that thinking?

 

[9949asd]

So Arrow Lake can do DDR5 Gear 1??

Shoudl that more than make up for the IMC being on a spearate tile form CPU corers and ring unlike Raptor and Alder? Raptor and Alder can only do DDR5 Gear 2, but they have faster IMC latency due to the IMC being on the same die on CPU cores and ring? Am I right on that thinking?

I don’t know it’s a bug or not. For the cudimm When showing 1:1 is g2, when showing 1:2 is g4.
For ARL there is no d4 inc anymore.

 

[Magio]

Hmm? I thought it was more dense.

If you read between the lines of Intel's own communication, this isn't a big surprise:

This is Intel's own assessment of how their nodes will fare against TSMC's, which logically you'd assume would have Intel pit 18A against TSMC's top of the line node when 18A is set for HVM.

"≈" in a marketing slide may as well mean "slightly worse", and 18A will reach HVM before N2 so TSMC's top of the line would be N3P at that point. So 18A having slightly worse density than N3P is the logical take away from this. But keep in mind N2 is "only" expected to have +/- 15% density uplift over N3E, so that's not actually too bad especially as 18A-P would bridge some of that gap again probably within reasonable timelines.

"+≈" on the other hand in marketing speech would most likely mean "maybe barely better but generally as good", so they expect 18A to fare well in PPW (at least in HPC scenarios) vs N3E/P and 14A to finally actually see them reclaim the density lead even if not by much.

Napkin math from SemiAnalysis' prediction that 18A will have a 50+% density uplift over Intel 3 would probably mean it should land a bit above 200MTr/mm² which is indeed a tad behind N3E/P.

 

[KompuKare]

On the 10th we'll have a good idea about productivity performance, and then 2 weeks of arguing about gaming performance will follow.

If gaming performance is very influenced by memory speeds above spec then those arguments may last a lot longer than 2 weeks!

 

[CouncilorIrissa]

LNL die shots.

https://twitter.com/x/status/1841497643178148185

 

[GTracing]

LNL die shots.

https://twitter.com/x/status/1841497643178148185

I measure the four P cores at 1632791 pixels with L3 cache and 1179648 pixels without L3. The four E cores are 441548 pixels. That makes the E cores 27% the size of the P cores with L3, or 37% the size of P cores without the L3. Good to see the increase in performance didn't balloon the E core's area.

 

[mvprod123]

 

[9949asd]

Geekwan lunar lake test
Limited board power to 30w and 15w, lunar lake crush every things.

 

[9949asd]

 

[511]

Lunar lake is really good except the mod MT perf at higher Power it's really a good chip and Snapdragon hype has been dead 🤣

 

[Abwx]

Geekwan lunar lake test
Limited board power to 30w and 15w, lunar lake crush every things.
View attachment 108556View attachment 108557View attachment 108559View attachment 108561View attachment 108562

First pics : 258V 22W soc power, HX370 15W.

Last pic : 258V 12W soc power, HX370 9W.

So that s just a tiny 50% more power.

Yeah, it crush everything when it comes to cheating.

View attachment 108565

Same here, 258V at 12W vs 9W for the 370, that s just a joke of a test.

 

[controlflow]

First pics : 258V 22W soc power, HX370 15W.

Last pic : 258V 12W soc power, HX370 9W.

So that s just a tiny 50% more power.

Yeah, it crush everything when it comes to cheating.



Same here, 258V at 12W vs 9W for the 370, that s just a joke of a test.

You clearly did not watch the video.

 

[DavidC1]

Napkin math from SemiAnalysis' prediction that 18A will have a 50+% density uplift over Intel 3 would probably mean it should land a bit above 200MTr/mm² which is indeed a tad behind N3E/P.

And they are completely wrong, ignoring Intel's own presentation that 18A offers mere 30% density improvement over Intel 3.

You clearly did not watch the video.

What else can you expect from him?

 

[mvprod123]

It's still worse in terms of power efficiency than the M1, which is 4 years old and made on a TSMC N5 node. It's amusing

 

[Abwx]

You clearly did not watch the video.

Power is stated on the captured screens, and yet he write that it s at 15W despite 22W
being displayed on the screen shots.

 

[cannedlake240]

And they are completely wrong, ignoring Intel's own presentation that 18A offers mere 30% density improvement over Intel 3.

TSMC N3 is also a mere 30% density increase over N5. Because it's chip density not logic density. Chips aren't made entirely out of highest density logic cells

 

[SiliconFly]

.

 

[adroc_thurston]

TSMC N3 is also a mere 30% density increase over N5

This doesn't have BSPDN or any other (new) scaling boosters.

 

[511]

And they are completely wrong, ignoring Intel's own presentation that 18A offers mere 30% density improvement over Intel 3.

Intel said Chip density they never said logic density two are different things
Chip density means Logic+Sram+Aanalog
Analog doesn't scale well Sram scaling is nearly dead for now

What else can you expect from him?

Yeah he is here to 🧌 don't mind him

 

[511]

This doesn't have BSPDN or any other (new) scaling boosters.

BSPDN has routing benefits and Droop benifits you can read Intel 4 + Power via

 

[adroc_thurston]

BSPDN has routing benefits and Droop benifits you can read Intel 4 + Power via

It has net density benefits. It's a scaling booster like many others.

 

[Det0x]

New coolers recommned for Arrow Lake

https://videocardz.com/newz/intel-core-ultra-200-lga-1851-cpu-hot-spot-reportedly-a-bit-further-north-than-lga-1700s

 

[DavidC1]

TSMC N3 is also a mere 30% density increase over N5. Because it's chip density not logic density. Chips aren't made entirely out of highest density logic cells

Please take a look at Lunarlake and tell me there's enough SRAM cells to change density improvements from 60% to 30% just because SRAM doesn't scale as well. Even if we assume SRAM improvement is 0%, it's a big stretch.

Daniel Nenni was guessing and he's wrong.