Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[cebri1]

Regarding the last few comments, what is the relative cost of an Intel versus a TSMC wafer for a comparable node? Unless this is known all these arguments are totally useless.

It's not known. However, if 18A ever takes off you can compare Gross Margins and more or less come up with an average price.

 

[KompuKare]

It's not known. However, if 18A ever takes off you can compare Gross Margins and more or less come up with an average price.

Fabs are so capital intensive that their fixed costs get written off over many multiple of years, so doesn't that mean annual gross margins are not enough to really deduce this?

 

[majord]

I agree should be around 2-3W range but knowing windows

Is it the minimum or it can even below LNL has tiles as well it shows superiority of the packing tech they possess

Minimum is a bit lower, but averaging around 0.6w over a few mins with all the sporadic occasional background processors firing up

(Balanced mode)

 

[cebri1]

Fabs are so capital introduce that their fixed costs get written off over many multiple of years, so doesn't that mean annual gross margins are not enough to really deduce this?

Are you sure? Investment in fixed assets (fabs and equipment) usually affect the operating margin, as you have to take into account the amortization of the assets. Gross margin is just the sale - the cost of that sale (mostly raw materials, direct labor cost, electricity, etc.).

edit: nvm I think you are right. Makes sense.

 

[KompuKare]

Are you sure? Investment in fixed assets (fabs and equipment) usually affect the operating margin, as you have to take into account the amortization of the assets. Gross margin is just the sale - the cost of that sale (mostly raw materials, direct labor cost, electricity, etc.).

Certainly not sure, anyways!

But with capital investments for which small countries would have to issue bonds for - that is billions upon billions - hiding stuff is easy.

Now the pure fabs well have time of old nodes and packaging plants and pure r&d over lots of factories making it really hard to see what is what.

Some of that is just the way it is, but some of it must be make things as opaque as possible so their clients cannot work how much each is paying etc.

 

[511]

Are you sure? Investment in fixed assets (fabs and equipment) usually affect the operating margin, as you have to take into account the amortization of the assets. Gross margin is just the sale - the cost of that sale (mostly raw materials, direct labor cost, electricity, etc.).

edit: nvm I think you are right. Makes sense.

Btw TSMC cost is also offset due yo lagging node that is just running on equipment and depreciation all it costs is yhe cost of operations of the equipment Intel didn't do that they kep N,N-1 where N is latest now they are moving away they already mixed 14nm into Intel 16
On a side note
I don't think 14nm will ever die 🤣

 

[SiliconFly]

.

 

[jdubs03]

It appears ARL (and maybe ARL-R) will be the last N3B based Intel products.

Source on that? Would seem to make sense. But oddly then there is this:

https://twitter.com/x/status/1833424280111222850

I would think they want to be using 18A by then.

Also Canadian pricing for ARL:

https://videocardz.com/newz/intel-core-ultra-200k-cpus-listed-in-canada-similar-pricing-to-14th-gen

 

[cannedlake240]

But oddly then there is this

More FUD and fearmongering. If this is true IFS is being dissolved right now. There's no recovering from a debacle of this magnitude. Best case is a merger with GF with government help

 

[SiliconFly]

.

 

[511]

Edit: Generally speaking, I'm pretty much convinced that IFS doesn't have much of a future considering their execution. Not blaming anyone in particular. Fabs are real hard, and trying to succeed at this break neck pace is bound to have issues. It's time for Intel to cut loose the dead weight.

If Intel Cuts fab time for US to accept they will loose to China in manufacturing 🤣

 

[cannedlake240]

Panther Lake both desktop

There is no Panther lake desktop, and it arrives later than Clearwater. Desktop is ARL-R with a larger NPU. Clearwater is the lead product for 18A, just as iphone chips are for leading edge TSMC nodes. If your lead product is outsourced all of a sudden, it means the node is completely unusable, and Intel failed to yield Ribbonfet and Powervia

 

[cebri1]

I don’t think the compute tiles for CWF will be outsourced to N3E. Maybe for some SKUs? to make sure enough volume is available if cloud providers are showing a lot of interest? but this is something that should have already been leaked, is not a decision you can make 3Q before release.

 

[511]

Nope here is the brief rest is Fud this month has been full of fud to force intels seperation

I don’t think think the compute tiles for CWF will be outsourced to N3E. Maybe for some SKUs? to make sure enough volume is available if cloud providers are showing a lot of interest, but this is something that should have already been leaked, is not a decision you can make 3Q before release.

 

[cebri1]

Nope here is the brief rest is Fud this month has been full of fud to force intels seperation

Yeah it’s a full Intel chip. I think he confused FS and CWF

Intel's next-gen Falcon Shores AI chip: ordered on TSMC 3nm node, CoWoS advanced packaging

Intel reportedly placed orders for its next-generation AI chip codenamed 'Falcon Shores' with TSMC, using its CoWoS advanced packaging, 3nm process node.

www.tweaktown.com

 

[511]

Yeah it’s a full Intel chip. I think he confused FS and CWF

Intel's next-gen Falcon Shores AI chip: ordered on TSMC 3nm node, CoWoS advanced packaging

Intel reportedly placed orders for its next-generation AI chip codenamed 'Falcon Shores' with TSMC, using its CoWoS advanced packaging, 3nm process node.

www.tweaktown.com

Also the advance packing is false in this rumour Intel will use their own advance packing

 

[cannedlake240]

Also the advance packing is false in thiss rumour Intel will yse their own advance packing

Nah that might actually be true because FCS is apparently derived from gaudi line that is fully outsourced

 

[511]

Nah that might actually be true because FCS is apparently derived from gaudi line that is fully outsourced

FCS is a combination of Gaudi + Xe3 anyway that would have been idiocity cause their packing tech is very good this way they will save few $

 

[jdubs03]

Yeesh well this isn’t a great result for the 265KF.

https://twitter.com/x/status/1833452761436041545

33153 samples for the 265K.
34500 samples for the 14700K.

 

[cebri1]

Yeesh well this isn’t a great result for the 265KF.

https://twitter.com/x/status/1833452761436041545

33153 samples for the 265K.
34500 samples for the 14700K.

No, the 14700K does 31525. About 6% faster but below expectations.

I’d wait for independent benchmarks. Without knowing the system configuration, bios, etc. it’s not that useful

 

[igor_kavinski]

I DEMAND to know why Intel couldn't cook up Dynamic SMT: https://www.ibm.com/docs/el/zvm/7.2?topic=architectures-simultaneous-multithreading-smt

If multithreading is enabled, the SET MULTITHREADcommand can be used to nondisruptively switch between one and twoactivated threads per IFL core. Performance of a system and workloadwith one active thread per core is comparable to that of the samesystem and workload with multithreading disabled. Thus, the dynamicSMT level capability allows the benefit of multithreading to be evaluatedfor a workload without requiring an outage to enable or disable SMT.

 

[MS_AT]

No, the 14700K does 31525. About 6% faster but below expectations.
View attachment 107204

for what it is worth

 

[cebri1]

View attachment 107205
for what it is worth

Mm that does make sense they are the same chip. Maybe more KF test were done under OC conditions?

 

[MS_AT]

I DEMAND to know why Intel couldn't cook up Dynamic SMT: https://www.ibm.com/docs/el/zvm/7.2?topic=architectures-simultaneous-multithreading-smt

While I can only guess, based on their own press materials, they wanted to save transistor budget. After all you need to duplicate some structures to support SMT and seeing professional software still has issues with Raptor Lake due to scheduling issues, it might be for the better for them to simplify the model. (Windows Containers default to running on E-cores and VMware is ignoring E cores completly I think, unless they maybe finally fixed it, hmm).

 

[cebri1]

https://videocardz.com/newz/intel-core-ultra-200k-launch-pushed-back-by-a-week-now-coming-october-24

Another packaging error? 🤔