Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[Josh128]

I get the throttling for MT. But for ST?
Time to throw it in the freezer!

If you remember, Strix had the same issue on the Zenbook models, not able to attain the full 5.1 boost, while the larger, better cooled ProArt has better cooling and hits the full SC boost.

 

[naukkis]

Still something not right. L2 are too slow. And for ARL everyone can use CUDIMM xmp 9200

L2 is actually L3 now so its latency see that intermediate 192kb cache latency added, which is about twice of L1. So seems to be just in line.

 

[MarkPost]

ST is not disappointing at all here. @5GHz it is beating Strix @5.1 by 8-10%. Its beating the newest, fastest x86 core available by 10%, what more do you want? MT is nothing special, but if this is at 17W, its ~passable. Strix gets 954 @28W with 12 cores.

dunno if Strix is slower than Granite, but zen 5 desktop scores ~128 pts. fixed @5.1 with DDR5 @6000 EXPO

 

[dullard]

Edit: Btw, I think someone also mentioned it. 20A being scrapped is probably because 18A with PowerVia had good enough yields, and 20A use was going to be limited (one ARL-S SKU that we know off). However, 18A is falling short on performance expectations (from around 25% improvement in perf/W over Intel 3 to only 15%). The new 18A-P node they added to the roadmap will have the expected additional 10% improvement, but I don't think that will be ready before end of 25, early 26.

I think something that has been missed in the last week of node discussions. It is that Intel changed 18A about a year ago (at least they confirmed the change a year ago). https://www.anandtech.com/show/2006...v-work-on-intel-18a-production-in-future-node

18A was originally going to be made with high-NA EUV. But they moved 18A from being manufacturing ready in 2025 to H2 2024 which is before high-NA EUV is ready: https://www.anandtech.com/show/1734...on-moves-up-intel-18a-manufacturing-to-h22024

This has two impacts:
(1) 18A will not be as advanced as originally planned by dropping high-NA EUV and pulling it up a half year earlier. Thus, they have 18A-P that uses more EUV. https://www.intel.com/content/www/u...es/foundry-direct-connect-2024.html#gs.evm56y Yield, and performance discussions should reflect that (don't use performance expectations from before the change).

(2) There is no longer much need for 20A. Since 18A was moved up half a year, since the risk of high-NA EUV was removed, and since 18A has low defect rates according to Intel, then 20A is just redundant. https://www.intel.com/content/www/us/en/newsroom/opinion/continued-momentum-intel-18a.html

As an aside: we should be clear to discuss defects with respect to which 18A we are talking about. 18A or 18A-P.

 

[DZero]

Intel should accelerate their 18A since relying too much in TSMC would put them in a similar situation AMD is.

 

[Josh128]

dunno if Strix is slower than Granite, but zen 5 desktop scores ~128 pts. fixed @5.1 with DDR5 @6000 EXPO

View attachment 107150

Probably due to some degree of thermal throttling still on the laptop, that and they say mem speed can affect R24 as well, so yet more uncertainty there.

 

[MS_AT]

Probably due to some degree of thermal throttling still on the laptop, that and they say mem speed can affect R24 as well, so yet more uncertainty there.

For what it is worth, desktop parts have twice as big L3 cache [32MB vs 16MB] but L3 is a victim cache so not sure how well R24 is able to make use of it.

 

[511]

Btw TSMC Said 18A is Comparable to N3P means superior to N3E but Intel 4 is closer to N4 and I3 is closer to N3B which makes Intel 18A closer to N2!!
Source

Intel 4 Deep Dive - Semiwiki

As I previously wrote about here, Intel is presenting their Intel 4 process at the VLSI Technology conference. Last Wednesday Bernhard Sell (Ben) from Intel gave the press a briefing on the process and provided us with early access to the paper (embargoed until Sunday 6/12). “Intel 4 CMOS...

semiwiki.com

 

[9949asd]

Intel should accelerate their 18A since relying too much in TSMC would put them in a similar situation AMD is.

I think intel should stay with TSMC for the msdt until they’re fab is better than tsmc(impossible).

 

[cannedlake240]

Intel 18A closer to N2!!

Intel still doesn't have proper dense logic cells. I3 HD is only 10% denser than i4 HP, meanwhile between TSMC N3 HP and HD, used by AI, iphones etc., there's a massive density difference.

Plus there's some rumors that high end NVL will still use N2. Lol even the next lake after NVL is apparently partially outsourced instead of using 14A, which is supposed to be the Intel's crown jewel

 

[511]

I think intel should stay with TSMC for the msdt until they’re fab is better than tsmc(impossible).

You mean comparable ? I don't understand people's problems with Intel Fab they got in that state due to BK and Swan BK gutted the funding and Swan didn't do anything after that to save it the only reason intel has such a scale is the fab do you know TSMC copied Intel untill intel F***** up good

 

[AcrosTinus]

I think intel should stay with TSMC for the msdt until they’re fab is better than tsmc(impossible).

You don't need to be better than TSMC, you just have to be competitive.
Intel 3 is good, 20A is internal and cancelled and 18A if the specs are to be believed, is great as well.

 

[511]

Intel still doesn't have proper dense logic cells. I3 HD is only 10% denser than i4 HP, meanwhile between TSMC N3 HP and HD, used by AI, iphones etc., there's a massive density difference.

Intel for it's Intent never uses HD they need to for their fab buisness but HPC is Intel's speciality also part of TSMC density is due to finflex allowing you to mix and match 2-2 2-1 fins that is what gives the density boost with tighter pitches 18 AP exists for this

Plus there's some rumors that high end NVL will still use N2. Lol even the next lake after NVL is apparently partially outsourced instead of using 14A, which is supposed to be the Intel's crown jewel

Rumours yeah sure i can get part of it is TSMC but not 100%

Btw Falcon shores is N3E their GPU is at TSMC with PTL they will bring some part of it to Intel 3

 

[511]

If TSMC says N3P is comparable to 18A you can at least trust TSMC more than Intel.

 

[Josh128]

Btw TSMC Said 18A is Comparable to N3P means superior to N3E but Intel 4 is closer to N4 and I3 is closer to N3B which makes Intel 18A closer to N2!!
Source

Intel 4 Deep Dive - Semiwiki

As I previously wrote about here, Intel is presenting their Intel 4 process at the VLSI Technology conference. Last Wednesday Bernhard Sell (Ben) from Intel gave the press a briefing on the process and provided us with early access to the paper (embargoed until Sunday 6/12). “Intel 4 CMOS...

semiwiki.com

So who is lying?

 

[SiliconFly]

.

 

[511]

So who is lying?

As silicon fly said N2 will be on par with 18A in PPW but will be ahead by 15-20% in terms of density vs 18A , 18A might be slightly cheaper than N2

 

[SiliconFly]

.

 

[controlflow]

That was a bit of a surprise to me too when Intel said 18A will be cheaper than N2! Considering the all new transistor with BSPDN, I'm not sure how it works cos the R&D cost itself will be thru the roof!

Intel Is All-In on Back-Side Power

The company’s PowerVia interconnect tech demonstrated a 6 percent performance gain

spectrum.ieee.org

"You might expect that having to build interconnects on both sides of the silicon would make the cost of the chip shoot up. But early on, Intel saw a reason why that would not be the case, says Sell. The smallest, most tightly packed layer of interconnects, called M0, are also the costliest to produce. They can require more than one pass through chipmaking’s most expensive step, extreme ultraviolet lithography. But with no power interconnects to get in the way, the lines in the M0 layer could be six nanometers further apart than they are today. That may not seem like much, but it means it takes less EUV effort to make them. For the process to be introduced next year and for its successor, “the cost savings we get from not scaling so aggressively more than offsets the additional cost from the backside power-delivery process,” Sell says."

 

[511]

Yup they reduced the pitches i don't know about EUV layers affect cost More layers means increasing cost that is why Intel 7 is a disaster it uses SAQP basically 4 time scanning and etching with DUV with EUV they would have gotten by single layer saving cost here is a good article

TSMC N3, And Challenges Ahead

A Look At TSMC N3 Process

fuse.wikichip.org

 

[Magio]

That was a bit of a surprise to me too when Intel said 18A will be cheaper than N2! Considering the all new transistor with BSPDN, I'm not sure how it works cos the R&D cost itself will be thru the roof!

I'm thinking the cost will be lower than N2 to the customers because Intel will set it as low as possible to attract them. TSMC doesn't really have to do that because they have clients to spare and Apple will buy up the entire N2 production for a year anyway. So the node isn't cheaper (don't see how it could be with GAAFETs, BSPDN and with US manufacturing), but Intel will not be seeking high margins to start getting contracts.

 

[desrever]

I'm thinking the cost will be lower than N2 to the customers because Intel will set it as low as possible to attract them. TSMC doesn't really have to do that because they have clients to spare and Apple will buy up the entire N2 production for a year anyway. So the node isn't cheaper (don't see how it could be with GAAFETs, BSPDN and with US manufacturing), but Intel will not be seeking high margins to start getting contracts.

Pricing it low will just bankrupt Intel.

 

[LightningZ71]

Not gaining market share will also bankrupt intel. Some revenue to cover fixed costs is better than no revenue...

 

[SiliconFly]

,

 

[maddie]

I'm thinking the cost will be lower than N2 to the customers because Intel will set it as low as possible to attract them.

Pricing it low will just bankrupt Intel.

Not gaining market share will also bankrupt intel. Some revenue to cover fixed costs is better than no revenue...

And, Intel has to price it lower than the competitor in order to survive. Doesn't mean they have to do it at a loss. More like they have go with reduced margins or a loss in profit if you prefer (or maybe even a slight loss). Far from bankruptcy.

Regarding the last few comments, what is the relative cost of an Intel versus a TSMC wafer for a comparable node? Unless this is known all these arguments are totally useless.