Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[CouncilorIrissa]

I don't know why anyone would expect anything else other than marginal ST uplift. Intel 7 is many things, but it allowed Intel to clock their CPUs incredibly high. Finding a large ST uplift was always going to be an uphill battle.

 

[DavidC1]

I don't know why anyone would expect anything else other than marginal ST uplift. Intel 7 is many things, but it allowed Intel to clock their CPUs incredibly high. Finding a large ST uplift was always going to be an uphill battle.

Raptorlake was not supposed to exist. It was supposed to be Alderlake->Meteorlake. Instead, we got a REFRESH of the supposedly-not-existing part.

So they were able to refine the chip endlessly, same as when original 14nm disappointed due to longer than expected 22nm refinements. Then it happened again with 14nm vs 10nm.

 

[SiliconFly]

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[Abwx]

Are you saying there is only one QS sample Intel uses? Can you prove that? Then why he doesn't share the clock speed, what's the problem?

If it can get to 250W then it means that clock speeds are healthy, otherwise it couldnt hit such a TDP.

Beside the GB5 SC score is comparable to LNL when you account for the theorical frequency, in GB5 LNL does about 2000 pts at 4.6-4.7, so 2455 pts at about 5.7 is right on the money.

 

[SiliconFly]

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[mikk]

Hard to say considering his poor track record. He maybe wrong yet again! But considering his claims that it's a QS, the benches are a bit appalling. Not saying it's definitely close to final. But it maybe. And thats the worry.


LNC isn't RPC. It was supposed to bring in more IPC.

Why he isn't using the real name of the sample? if it's a 285K QS why not call it 285K QS? If it has 0000 CPU ID it's certainly not a QS.

 

[SiliconFly]

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[Abwx]

But, ARL's LNC was expected to have higher IPC than LNL's LNC. Otherwise, there was no necessity for 2 different LNCs. No reason to work on 2 expensive designs parallel. Something's amiss.

If no decent uplift, the P core team needs to be fired.

I m not familiar with all Intel s iterations but i dont think that they designed two different P cores, there could be very minor differences such as L3 cache size but for the rest this should be the same cores, otherwise that would be a nightmare for validation, better to deal with a single beast given that they have two designs within an hybrid uarch, that s already miraculous that these can be designed and fabbed in a matter of 2 years.

 

[Hitman928]

But, ARL's LNC was expected to have higher IPC than LNL's LNC.

From everything I've seen, that was simply a forum theory based on very shaky, if any, evidence.

Otherwise, there was no necessity for 2 different LNCs. No reason to work on 2 expensive designs parallel. Something's amiss.

They still need to design for LNL and ARL SoCs separately as they are supposed to compete in very different markets. However, that doesn't mean the cores themselves have changed at all, except maybe in higher levels of cache.

If no decent uplift, the P core team needs to be fired.

The P-core team has definitely been struggling.

 

[adroc_thurston]

From everything I've seen, that was simply a forum theory based on very shaky, if any, evidence.

It has 0.5M moar L2.
That'll have some, albeit marginal, impact.

 

[SiliconFly]

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[Hitman928]

It has 0.5M moar L2.
That'll have some, albeit marginal, impact.

Yes, I mentioned this in the next line, but the forum theory was that they were changing key structures of the cores themselves.

They've had way too much time since the last big tock. It was already mentioned clearly that LNC is an umbrella term for multiple core designs that share a common trait (fubs/cells). And ARL's LNC was expected to have more IPC than LNL's LNC not just due to cache/memory, but maybe due to a few other higher power/frequency related optimizations.

Usually around 5% was the expectations. I even expected more. But this changes the game entirely. Either many of us here were wrong, or the there's something off with the results. Need more info.

Again, unless you can show otherwise, this was just pure forum speculation that multiple people were debunking along the way, but I guess hopium kept it alive in the minds of some. Some later server offerings might differ in some respects to the consumer chips, but that wouldn't be anything new as Intel has made architectural tweaks for server SKUs on multiple occasions.

 

[SiliconFly]

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[Abwx]

They've had way too much time since the last big tock. It was already mentioned clearly that LNC is an umbrella term for multiple core designs that share a common trait (fubs/cells). And ARL's LNC was expected to have more IPC than LNL's LNC not just due to cache/memory, but maybe due to a few other higher power/frequency related optimizations.

Usually around 5% was the expectations. I even expected more. But this changes the game entirely. Either many of us here were wrong, or the there's something off with the results. Need more info.

Not so long ago 5% better IPC mandated a uarch serious overhaul despite lower hanging fruits than what is available nowadays.

Even if there s a little IPC difference between ARL and LNL this is partly leveled by the latter s huge 8533Mt/s RAM speed, that s 42% more BW than DDR5 6000, so in practice both chips should have comparable perf/Hz.

 

[carancho]

I don't know why anyone would expect anything else other than marginal ST uplift. Intel 7 is many things, but it allowed Intel to clock their CPUs incredibly high. Finding a large ST uplift was always going to be an uphill battle.

Plus it makes sense for Intel to choose a point in the curve that (barely) improves on their previous product while directing all efficiency+IPC improvements towards curtailing their insane power requirements. Otherwise they're never going to climb down from up there.

 

[CouncilorIrissa]

Ok. Here are my thoughts... @Jaykihn QS results may not reflect final. Either his QS isn't close to final or something else is amiss like bios, power profile, device drivers, memory, etc. He maybe wrong yet again. It just can't be this bad considering the heavy duty uplift provided by 16 skymont cores.

Even with all the additional high uplift provided by 16 skymont cores, if the total MT isn't good enough, then it kinda signifies that the P cores have serious IPC regression which doesn't compute well. Like I said, somethings amiss.

Time for some napkin math.

It's almost as if there's some feature that boosts your nT performance at a very small area cost that Intel dropped this gen.

 

[DavidC1]

Usually around 5% was the expectations. I even expected more. But this changes the game entirely. Either many of us here were wrong, or the there's something off with the results. Need more info.

I told you so...?

The only difference in the two cores are the 0.5MB L3 cache, meaning basically 0% gains.

If no decent uplift, the P core team needs to be fired.

Is there a middle ground with you? You flip completely from optimism to pessimism.

By the way, firing is what got them into this mess in the first place.

Even if there s a little IPC difference between ARL and LNL this is partly leveled by the latter s huge 8533Mt/s RAM speed, that s 42% more BW than DDR5 6000, so in practice both chips should have comparable perf/Hz.

ST doesn't care about bandwidth. Desktops have an advantage of having 60ns memory versus ~110ns for laptops which will actually matter for ST.

 

[pepeo]

If these leaks come out as true, lion cove seems disapointing, arrow lake seems meh even with the chadmont onboard. Tsmc 3nb, no avx512 and bigger core than z5 for overall similar perf and eficiency? Doesnt seems great for me

 

[H433x0n]

And ARL's LNC was expected to have more IPC than LNL's LNC not just due to cache/memory, but maybe due to a few other higher power/frequency related optimizations.

Usually around 5% was the expectations. I even expected more. But this changes the game entirely. Either many of us here were wrong, or the there's something off with the results. Need more info.

That was never the consensus viewpoint. There was never any evidence to expect anymore than 1-2% IPC over LNL’s version of Lion Cove.

The info that Intel provided to their partners was 1.05x over RPL. That should have always been the expectation.

 

[Goop_reformed]

Intel is back with their yearly schedule. single digit uplift is embarrassing. What are they even doing over there? 3 generations of Alderlake derivatives for this?

 

[H433x0n]

If these leaks come out as true, lion cove seems disapointing, arrow lake seems meh even with the chadmont onboard. Tsmc 3nb, no avx512 and bigger core than z5 for overall similar perf and eficiency? Doesnt seems great for me

TSMC N3B doesn’t provide any tangible benefit to an x86 core in a desktop CPU. I could even make an argument that N4P is a better node for that use case.

As far as efficiency goes, there’s still no data on this from either Zen 5 or ARL.

 

[H433x0n]

Intel is back with their yearly schedule. single digit uplift is embarrassing. What are they even doing over there? 3 generations of Alderlake derivatives for this?

If it’s competitive with Zen 5, does that mean Zen 5 by transitive properties is also embarrassing?

 

[adroc_thurston]

this is partly leveled by the latter s huge 8533Mt/s RAM speed, that s 42% more BW than DDR5 6000,

CPU fabric doesn't deliver full bandwidth on neither LNL or MTL/ARL CPU side.

TSMC N3B doesn’t provide any tangible benefit to an x86 core

That's cope, it's a marginally faster node under all circumstances.
It's just expensive, that's the downside.

 

[Goop_reformed]

If it’s competitive with Zen 5, does that mean Zen 5 by transitive properties is also embarrassing?

Competitive at what cost? New nodes, 2 new cores for that? Pyrrhic victory, and even that is not guaranteed.

 

[H433x0n]

Competitive at what cost? New nodes, 2 new cores for that? Pyrrhic victory, and even that is not guaranteed.

That same argument works in reverse too. It's super weird how Company A and Company B can land at the same performance and yet it's a disaster for one and a success for the other.