Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[PJVol]

It would have been more interesting If they compared Strix at 30W.
Not a bad performance in TimeSpy, but I still think RTX 3050 will be faster in games, thanks to much higher BW and let's nor forget Ampere is older tech

No one seems to mind that LNL iGPU performance shown in two least representative 3DMark tests, TS and WLE.
At least with ARC, TS score has little to do with gaming performance. The same goes for Nomad

The Fire Strike Extreme is way more suitable for comparing Intel and AMD GPUs in real-world gaming tasks.

 

[SmokSmog]

https://wccftech.com/amd-ryzen-9000x3d-cpus-full-overclocking-support-new-3d-v-cache-features/

You must provide some personal commentary when dropping links or pictures.
Also, this is an Intel thread so please keep the AMD links out.

Daveybrat
AT Moderator

 

[SiliconFly]

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[inf64]

View attachment 102100

(From X/Twitter)

LNC has tons of improvement. We can expect a good ST uplift in ARL.

Well we already have ~14% IPC number directly from intel where they compare it to Redwood cove (which is ~3% slower than Raptor cove). Not sure what you consider "a good ST uplift"? If it can clock to ~5.8Ghz ST and does ~15% better than Raptor lake IPC wise (being generous here considering the previous IPC disclosure), it will have ~7-8% better ST performance.

 

[SiliconFly]

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[inf64]

Leaks strongly suggest Arrow Lake's LNC is different from Lunar Lake's LNC. That 14% uplift you mention is Lunar Lake's LNC w.r.t Redwood Cove. Expecting a lot more ST uplift from Arrow Lake's LNC. Even after adjusting for clock regression, we should be left with at least 15% more ST perf (maybe even upto 20%... who knows).

You are basing this all on fate I guess? I have seen zero stuff from anyone reputable that will suggest any big deviation in IPC going to ARL. Even the slides mentioned the optimizations in LNL LionCove were to maximize the ST performance of the core by getting rid of HT related structures.

Just to let you know, in order to get up to 20% ST uplift vs Raptor Cove, you would need almost 30% ST IPC uplift and 5.8Ghz ST clock. 30% IPC uplift is not gonna happen, there is no magic bullet that will make ARL version of LionCove gain 15% more IPC vs LNL version.

 

[coercitiv]

Leaks strongly suggest Arrow Lake's LNC is different from Lunar Lake's LNC.

Apart from the bigger L2, what else do leaks "strongly suggest" is different?

LNC in LNL benefits from an on-die memory controller. MTL has the memory controller on the SoC. How's Arrow Lake going to fare in this regard, is the overall structural layout the same as MTL, with the mem controller still situated on the other tile?

 

[SiliconFly]

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[ondma]

There has been discussion already stating that Lion Cove is not a single architecture, but an umbrella term for a group of designs based on a larger blueprint. Remember "Sea of Fubs to a Sea of Cells".

The P core team in their video clearly said that they've moved not only to industry standard design tools, but now the design is also process agnostic and also now they can rapidly slice and dice the design as they wish.

With so much of power and flexibility at their disposal, I don't think they're gonna just release the same LNC yet again with ARL (defeats the entire purpose). And it also aligns well with the initial rumors as well.

You can always claim they didn't explicitly state ARL's LNC will be different from LNL's LNC. But at the same time, I can also claim that they didn't explicitly state ARL's LNC will be the same as LNL's LNC. The jury is still out on that one.

And looking at all the published info, I believe ARL's LNC is gonna be more different than some assume it to be. 20% IPC uplift over RWC is entirely possible. Maybe more if they've done something cool.

Rental Units would be '"cool". ARL 8+32 would be interesting. Beast Lake 16+32 would be a killer. Royal Core might be cool. Will we ever see any of them? Seems like every time Intel supposedly has something "cool" in the pipeline it either is late, gets cancelled, or simply does not live up to the hype. Point being? Just because Lion Cove is potentially a flexible architecture, considering the way Intel has executed lately, I certainly don't expect them to pull some magic out of the hat and give LC in ARL more than a token increase in IPC compared to the same core in LL. At best perhaps they will be able to make some modifications to Lion Cove in RL-R to make it more performant.

 

[AcrosTinus]

Rental Units would be '"cool". ARL 8+32 would be interesting. Beast Lake 16+32 would be a killer. Royal Core might be cool. Will we ever see any of them? Seems like every time Intel supposedly has something "cool" in the pipeline it either is late, gets cancelled, or simply does not live up to the hype. Point being? Just because Lion Cove is potentially a flexible architecture, considering the way Intel has executed lately, I certainly don't expect them to pull some magic out of the hat and give LC in ARL more than a token increase in IPC compared to the same core in LL. At best perhaps they will be able to make some modifications to Lion Cove in RL-R to make it more performant.

This smug MLID way of dismissing a company based on not realized hype and rumors is not fair. A heavy research and development company like Intel will have successful stuff in the lab and stuff that is nice but not economical. (Rest in peace 3DXPoint, you somehow made it through the beancounters but too soon to be appreciated)

The Advancement Intel made on Lion Cove allows them to easier iterate and customize for a particular use case, this is another de-risking strategy from Pat. The nodes don't lock anymore due to standardized tools and possible TSMC outsourcing.

Fingers crossed for a 10+% increase in ST performance each year which would mean 30% or more in a 3Y upgrade cycle, this is great.

 

[SiliconFly]

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[SiliconFly]

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[majord]

There has been discussion already stating that Lion Cove is not a single architecture, but an umbrella term for a group of designs based on a larger blueprint. Remember "Sea of Fubs to a Sea of Cells".

The P core team in their video clearly said that they've moved not only to industry standard design tools, but now the design is also process agnostic and also now they can rapidly slice and dice the design as they wish.

Everyone does this already.. If there was some solid info that the version of Lion cove in Lunar Lake was some sort of cut down variant of a larger core , then maybe it would be worth speculating. Assuming they can just throw things arbitrarily at the core to pull meaningful IPC [general] gains is a bit 'pie in the sky'.

 

[CouncilorIrissa]

There has been discussion already stating that Lion Cove is not a single architecture, but an umbrella term for a group of designs based on a larger blueprint. Remember "Sea of Fubs to a Sea of Cells".

The P core team in their video clearly said that they've moved not only to industry standard design tools, but now the design is also process agnostic and also now they can rapidly slice and dice the design as they wish.

With so much of power and flexibility at their disposal, I don't think they're gonna just release the same LNC yet again with ARL (defeats the entire purpose). And it also aligns well with the initial rumors as well.

You can always claim they didn't explicitly state ARL's LNC will be different from LNL's LNC. But at the same time, I can also claim that they didn't explicitly state ARL's LNC will be the same as LNL's LNC. The jury is still out on that one.

And looking at all the published info, I believe ARL's LNC is gonna be more different than some assume it to be. 20% IPC uplift over RWC is entirely possible. Maybe more if they've done something cool.

I think there's little reason to have two significantly different core designs on client.
I personally think it's server where LNC will be at its most different compared to LNL, rather than ARL, much like Skylake-SP had a different L2 and support for AVX-512 that was missing from Skylake-S.

 

[Hulk]

I think there's little reason to have two significantly different core designs on client.
I personally think it's server where LNC will be at its most different compared to LNL, rather than ARL, much like Skylake-SP had a different L2 and support for AVX-512 that was missing from Skylake-S.

Maybe with the addition of HT for server as well.

 

[Hulk]

Lunar Lake is going to be a big improvement for small form factor laptops. Imagine a low power laptop with 8 Raptor Cove cores. Pretty good. Now imagine 4 Lion Cove + 4 Raptor Cove. Even better. Top of the stack parts might well compete with the 14500.

 

[ondma]

Possibly a bit more than that.


I'm guessing Lion Cove in ARL-R. It's always a possibility. But it's a bit too far.

I meant ARL-R for improved Lion Cove of course (too many lakes). I too had thought that Intel was back on track and executing well. However, the somewhat disappointing Meteor Lake release, the fact that they had to do a Raptor lake refresh instead of having a new architecture, and the stability problems with 13th and 14th gen (and the lack of a quick fix) are putting a lot of doubt back in my mind.

 

[TwistedAndy]

LNC in LNL benefits from an on-die memory controller. MTL has the memory controller on the SoC. How's Arrow Lake going to fare in this regard, is the overall structural layout the same as MTL, with the mem controller still situated on the other tile?

Lunar Lake is similar to Meteor Lake in this regard. Intel removed the memory controller from the P-core ring to have an option to shut down the whole P-core cluster.

Arrow Lake will have the memory controller on the ring as we have on Alder Lake and Raptor Lake. If we compare Lion Cove in Lunar Lake and Arrow Lake, there will be ~ a 5% difference in terms of IPC, mostly because of larger caches and faster memory with lower latencies.

I personally think it's server where LNC will be at its most different compared to LNL, rather than ARL, much like Skylake-SP had a different L2 and support for AVX-512 that was missing from Skylake-S.

Yep. One of the reasons why Intel has switched to a new design approach is to be able to easily toggle some features on the hardware level. There is no sense in spending the die space and power budget on the AVX-512 support on hybrid platforms. Another toggle is the HT support.

Both AVX-512 and HT will be available for workstation and server SKUs.

 

[coercitiv]

Arrow Lake will have the memory controller on the ring as we have on Alder Lake and Raptor Lake.

So the mem controller is moved to the compute tile? Because AFAIK MTL not only has the mem controller off the ring, it's on the SoC tile too.

 

[Kepler_L2]

Arrow Lake will have the memory controller on the ring as we have on Alder Lake and Raptor Lake.

No

 

[TwistedAndy]

So the mem controller is moved to the compute tile? Because AFAIK MTL not only has the mem controller off the ring, it's on the SoC tile too.

Lunar Lake and Meteor Lake share the same concept: the P-cores (a CPU cluster) and the GPU can be dynamically turned off to save power. That's why Intel moved the memory controller, LP E-cores, media engine, and other stuff to the SoC tile/cluster, which is always active.

There's no big difference in how those structures are implemented: as a separate tile (Meteor Lake) or an independent cluster (Lunar Lake).

In Meteor Lake Intel has introduced the NOC fabric to connect all the blocks:



In Lunar Lake, the structure will be very similar, but in addition to the memory controller, we will have the Side Cache (SLC). It will probably be something like a buffer for a memory controller. That will explain why they are placed closely on the actual chip.

From my perspective, in Arrow Lake, it makes sense to use the memory controller on the ring because there is no urgent need to turn off the P-core cluster or a GPU complex.

But Intel may want to use the NOC fabric on Arrow Lake as well. In this case, we can have LP E-cores, Side Cache, and other stuff on Arrow Lake.

We'll get more details on Intel's decision in August.

 

[DavidC1]

Mind you folks, that Computex crashed the "IPC" dreams of both Intel and AMD folks.

Memory bandwidth is a situational improvement when it comes to general purpose compute. Memory latency on the other hand is different, but it also needs to be significant improvement.

There seems to be a minor Zen 5-level hype people are trying to build up with Arrowlake's Lion Cove. There's nothing that suggests the improvement will be anywhere significant. Especially when Arrowlake inherits the Meteorlake's configuration.

I am expecting 2-3% best-case-scenario for Arrowlake, and for average, essentially zero.

@TwistedAndy There's little in common between LNL and MTL except both are using "Tiles" and both are made by Intel. Arrowlake INHERITS Meteorlake's configuration.

Some things in Arrowlake are a straight up downgrade such as the ACM+ based graphics tile.

I meant ARL-R for improved Lion Cove of course (too many lakes). I too had thought that Intel was back on track and executing well. However, the somewhat disappointing Meteor Lake release, the fact that they had to do a Raptor lake refresh instead of having a new architecture, and the stability problems with 13th and 14th gen (and the lack of a quick fix) are putting a lot of doubt back in my mind.

Keep in reminder that development cycles can take 3-4 years, often more. Meteorlake is the effect of BK's management starting in 2014.

It is much easier to break something than to repair it or make it. At some point in development the only thing even a stellar management can manage to do is stop the delays from getting worse.

Sierra Forest, Lunar Lake, and other products coming out NOW will determine the strength of Gelsinger's management. The more time passes, more will fall on him, good or bad.

 

[TwistedAndy]

@TwistedAndy There's little in common between LNL and MTL except both are using "Tiles" and both are made by Intel. Arrowlake INHERITS Meteorlake's configuration.

Here's the Lunar Lake layout:



We have mostly the same configuration as Meteor Lake with the NOC fabric joining LP E-cores cluster, P-cores cluster, NPU, Media, GPU, IO-tile (at the bottom), and Side Cache as a buffer for the memory controller.

The main difference is the organization of P-cores (MTL has a P- and E-core CPU cluster), the number of E-cores, and the Side Cache, which buffers the memory.

But yes, In Arrow Lake, we will have a CPU cluster similar to Meteor Lake and, probably, with a similar NOC fabric and Side Cache.

 

[SiliconFly]

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[coercitiv]

We have mostly the same configuration as Meteor Lake with the NOC fabric joining LP E-cores cluster, P-cores cluster, NPU, Media, GPU, IO-tile (at the bottom), and Side Cache as a buffer for the memory controller.

AFAIK in MTL the CPU cores are connected via a ring bus, with the SoC tile having a ring stop to collect traffic that is then passed to the SoC NOC fabric. If this is true, then calling it "mostly the same configuration" is a bit forced.

Spoiler

Granted the part about he SoC ring stop is based on some assumptions by Chips and Cheese, if there's more up-to-date info on the subject it would be great if folks could share a link.