Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[SiliconFly]

Nova Lake might be on Intel 14A & TSMC N2.

 

[FlameTail]

Nova Lake is 2026?

Also why TSMC N2, if they have better IFS nodes?

 

[S'renne]

I am expecting upcoming NovaLake - H with LPDDR6 support will include big iGPU like Halo. Panther Lake already has 12XE GPU, thus NVL-H should have 20XE, ie 320EU.....sound familar?

That is so late damn...just asking since alternatives or competitive products would still be good for the market

 

[DavidC1]

I am expecting upcoming NovaLake - H with LPDDR6 support will include big iGPU like Halo. Panther Lake already has 12XE GPU, thus NVL-H should have 20XE, ie 320EU.....sound familar?

20 Xe cores in 2027 is not big. Big would be 40 or 50 Xe cores.

Arrow - Early 2025
Panther - Early 2026
Nova - Early 2027

8 Xe cores = 16 CU
20 Xe cores = 40 CU

Yay, 2027 Intel iGPU rivals soon-to-be released Strix Halo. It's 3 years from now. Somebody remind us what was available in early 2021?

Nova Lake is 2026?

Also why TSMC N2, if they have better IFS nodes?

Because MLID?

 

[S'renne]

Can't they just use Arrow Lake to compete with Strix Halo

 

[Tigerick]

20 Xe cores in 2027 is not big. Big would be 40 or 50 Xe cores.

Arrow - Early 2025
Panther - Early 2026
Nova - Early 2027

8 Xe cores = 16 CU
20 Xe cores = 40 CU

Yay, 2027 Intel iGPU rivals soon-to-be released Strix Halo. It's 3 years from now. Somebody remind us what was available in early 2021?


Because MLID?

Clearly you have no ideas about memory bandwidth. FYI, upcoming Battlemage GPU comes with 32 Xe cores and 256-bit 20Gbps GDDR6 memory, ie 640GB/s BW. Even with LPDDR6, 128-bit only translate into 205 GB/s, one third of the GDDR6, 20 Xe cores actually sounds generous cause I am counting ADM to help with memory limitation.

And don't you know Intel is always late to party? Panther Lake with similar specs to Strix Point is one and half year later, go figure...

 

[Tigerick]

Nova Lake is 2026?

Also why TSMC N2, if they have better IFS nodes?

Just like ARL-S is using N3B not 18A, you have so much to know about IFS later

 

[ondma]

Just like ARL-S is using N3B not 18A, you have so much to know about IFS late

Nobody has ever said ARL will use 18A. Gelsinger recently said again that ARL will use 20A.
Here is a reference: https://www.tweaktown.com/news/95818/intels-arrow-lake-cpus-on-target-for-2024-launch-ceo-asserts-with-massive-ai-gains-in-tow/index.html

Edit: somehow the link may not work, it doesnt for me. In any case, the article is recent, and Gelsinger specifically says about halfway through the article that ARL is "our lead 20A vehicle".

 

[Hitman928]

Nobody has ever said ARL will use 18A. Gelsinger recently said again that ARL will use 20A.
Here is a reference: https://www.tweaktown.com/news/95818/intels-arrow-lake-cpus-on-target-for-2024-launch-ceo-asserts-with-massive-ai-gains-in-tow/index.html

Edit: somehow the link may not work, it doesnt for me. In any case, the article is recent, and Gelsinger specifically says about halfway through the article that ARL is "our lead 20A vehicle".

ARL compute tile will use 20A on some SKUs, but most of the volume will be on TSMC's N3B according to rumors + leaked document.

 

[SiliconFly]

Can't they just use Arrow Lake to compete with Strix Halo

They are.

 

[AMDK11]

What do you think about these RaptorLake-S 257mm2 and 26 billion transistors?

https://www.quora.com/The-Intel-i9-processor-has-a-transistor-count-of-about-4-2-billion-whilst-the-M1-Max-is-about-57-billion-How-come-their-performance-is-comparable

 

[Philste]

What do you think about these RaptorLake-S 257mm2 and 26 billion transistors?

Never ever. That would be above Intel 7s HD Density, and Intel is known to use low density Designs. Sapphire Rapids is 11B transistors per 400mm^2 if I remember correctly.

 

[dullard]

Totally understand, just seems like a waste of an EUV node to be using it on cache. That is, unless Intel 7 just can't accommodate TSVs, which I would find surprising.

The base is cache + interconnect network + voltage regulators, not just cache.

Intel said that they are trying to use the most advanced node for each component that doesn't go past the point of diminishing returns. That is, their best node for the cores will be 18A. Their best node for their base is Intel 3 (Intel 20A and 18A did not give much added performance for those components). The I/O will be on Intel 7 (not even Intel 4) as I/O just doesn't gain much from smaller nodes.

One could argue the exact point where the point of diminishing returns is located, but Intel seems to think they have something to gain at Intel 3 for the base. It might also be based on the fact that they are trying to increase production of Intel 3 and have very few products using it yet. If the lines are sometimes empty, might as well run them even if the gains are not too much.

As for adding the TSV technology to Intel 7, it seems like a lot to do for little to no gain on an aging node.

 

[AMDK11]

Never ever. That would be above Intel 7s HD Density, and Intel is known to use low density Designs. Sapphire Rapids is 11B transistors per 400mm^2 if I remember correctly.

I found this entry on Twitter:

https://twitter.com/x/status/1495821855667671041

"Some news for Sapphire Rapids from ISSCC: According to Nevine Nassif, Principal Engineer for Sapphire Rapids at Intel, the die size is a little lower than 400 mm² and the transistor count is between 11 and 12 billion."

 

[SiliconFly]

The base is cache + interconnect network + voltage regulators, not just cache.

Intel said that they are trying to use the most advanced node for each component that doesn't go past the point of diminishing returns. That is, their best node for the cores will be 18A. Their best node for their base is Intel 3 (Intel 20A and 18A did not give much added performance for those components). The I/O will be on Intel 7 (not even Intel 4) as I/O just doesn't gain much from smaller nodes.

One could argue the exact point where the point of diminishing returns is located, but Intel seems to think they have something to gain at Intel 3 for the base. It might also be based on the fact that they are trying to increase production of Intel 3 and have very few products using it yet. If the lines are sometimes empty, might as well run them even if the gains are not too much.

As for adding the TSV technology to Intel 7, it seems like a lot to do for little to no gain on an aging node.

Also, I think they can't use Intel 4 for base tile due to lack of denser libraries needed for cache.

 

[DavidC1]

Clearly you have no ideas about memory bandwidth. FYI, upcoming Battlemage GPU comes with 32 Xe cores and 256-bit 20Gbps GDDR6 memory, ie 640GB/s BW. Even with LPDDR6, 128-bit only translate into 205 GB/s, one third of the GDDR6, 20 Xe cores actually sounds generous cause I am counting ADM to help with memory limitation.

And don't you know Intel is always late to party? Panther Lake with similar specs to Strix Point is one and half year later, go figure...

What the heck are you on man?

It takes 8 Xe cores to compete with 12 CU(I got the 16CU wrong). AMD will have 40 CU Strix Halo soon.

Therefore, 20 Xe cores = 30 CU. Tell me that AMD won't increase mainstream iGPU from 12 in 2027? 20 Xe in 2027 is not a big deal, when AMD will have 26 Xe equivalent very soon.

 

[Tigerick]

英特爾執行長基辛格鬆口 關鍵CPU釋單台積 | 聯合新聞網

英特爾執行長基辛格21日親口證實，英特爾將把兩款處理器最關鍵的CPU晶片塊（Tile）首度交給台積電生產。這意味業界與外...

udn.com

According to UDN, Pat confirmed at IFS Direct Connect that Intel going to ask TSMC to make 2 CPU tiles, namely Arrow Lake and Lunar Lake.

 

[DavidC1]

One could argue the exact point where the point of diminishing returns is located, but Intel seems to think they have something to gain at Intel 3 for the base. It might also be based on the fact that they are trying to increase production of Intel 3 and have very few products using it yet. If the lines are sometimes empty, might as well run them even if the gains are not too much.

Yea, a 60%+ density for SRAM.

Intel is only scaling great on cache because TSMC is far ahead for SRAM and they hit limitations earlier, just like the reason DRAM is on 1xnm process forever is because they are fraction of SRAM(I mean like 20-30x difference) and hit limitations way earlier.

We'll see how Intel does on 18A.

 

[ondma]

ARL compute tile will use 20A on some SKUs, but most of the volume will be on TSMC's N3B according to rumors + leaked document.

So "rumors" and "leaked documents" (when and by whom?) are more reliable that what Gelsinger says? Honestly, they may be, but personally, I am not convinced by either the rumors or what Gelsinger says. We will have to just wait and see. I will be a very bad look for Intel's foundry business if the bulk of ARL is on TSMC silicon though.

 

[Tigerick]

So "rumors" and "leaked documents" (when and by whom?) are more reliable that what Gelsinger says? Honestly, they may be, but personally, I am not convinced by either the rumors or what Gelsinger says. We will have to just wait and see. I will be a very bad look for Intel's foundry business if the bulk of ARL is on TSMC silicon though

See above link, yeah it is from Taiwan news. Western news pretty soon will pick up...

 

[DavidC1]

So "rumors" and "leaked documents" (when and by whom?) are more reliable that what Gelsinger says? Honestly, they may be, but personally, I am not convinced by either the rumors or what Gelsinger says. We will have to just wait and see. I will be a very bad look for Intel's foundry business if the bulk of ARL is on TSMC silicon though.

It'll only look bad for a short time.

PantherLake with similar specs to Strix Point is one and half year later, go figure...

Another thing, I never alluded to Pantherlake beating Strix(although I believe it will), which should have been clear by "2027" remark but apparently your bias blinds you, since most points I made were about 20 Xe not being a "big deal".

 

[mikk]

What the heck are you on man?

It takes 8 Xe cores to compete with 12 CU(I got the 16CU wrong). AMD will have 40 CU Strix Halo soon.

Therefore, 20 Xe cores = 30 CU. Tell me that AMD won't increase mainstream iGPU from 12 in 2027? 20 Xe in 2027 is not a big deal, when AMD will have 26 Xe equivalent very soon.

You can't simply compare Xe1 with Xe2 and Xe3 and assume nothing will change. And who says Nova Lake gets 20 Xe cores, this is just a guess from someone. Strix Halo might be irrelevant for mobile, better wait and see. If this thing costs 3k up and comes with dGPU and tiny volume who cares. Strix Point is what really matters for mobile.

 

[Glo.]

What the heck are you on man?

It takes 8 Xe cores to compete with 12 CU(I got the 16CU wrong). AMD will have 40 CU Strix Halo soon.

Therefore, 20 Xe cores = 30 CU. Tell me that AMD won't increase mainstream iGPU from 12 in 2027? 20 Xe in 2027 is not a big deal, when AMD will have 26 Xe equivalent very soon.

Strix Halo is a 256 bit part. Its a completely different beast.

20 Xe core part most likely still will be 128 bit, same as that 12 Xe core part.

Thats the first thing.

Secondly they will be different architecture - Battlemage, instead of Alchemist. The performance/core will change.

Im willing to say that Intel will catch up to AMD with perf/ALU. At least to AMD.

 

[igor_kavinski]

Im willing to say that Intel will catch up to AMD with perf/ALU. At least to AMD.

Their graphics engineers/architects are under a lot more pressure to perform to keep their jobs.

Their CPU division is full of fat, lazy slobs who haven't faced any repercussions so far (that we know of) after the release of RPL-R and Crater Lake.

 

[mikk]

Strix Halo is a 256 bit part. Its a completely different beast.

20 Xe core part most likely still will be 128 bit, same as that 12 Xe core part.

Thats the first thing.

Secondly they will be different architecture - Battlemage, instead of Alchemist. The performance/core will change.

Im willing to say that Intel will catch up to AMD with perf/ALU. At least to AMD.

Nova Lake should have a Celestial iGPU at the very least given that Panther Lake seems to get Xe3 and comes 1 year earlier.