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Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

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Tigerick

Senior member
Wildcat Lake (WCL) Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing Raptor Lake-U. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q1 2026.

Intel Raptor Lake UIntel Wildcat Lake 15WIntel Lunar LakeIntel Panther Lake 4+0+4
Launch DateQ1-2024Q2-2026Q3-2024Q1-2026
ModelIntel 150UIntel Core 7 360Core Ultra 7 268VCore Ultra 7 365
Dies2223
NodeIntel 7 + ?Intel 18-A + TSMC N6TSMC N3B + N6Intel 18-A + Intel 3 + TSMC N6
CPU2 P-core + 8 E-cores2 P-core + 4 LP E-cores4 P-core + 4 LP E-cores4 P-core + 4 LP E-cores
Threads12688
Max Clock5.4 GHz4.8 GHz5 GHz4.8 GHz
L3 Cache12 MB6 MB12 MB12 MB
TDP15 - 55 W15 - 35 W17 - 37 W25 - 55 W
Memory128-bit LPDDR5-520064-bit LPDDR5x-7467128-bit LPDDR5x-8533128-bit LPDDR5x-7467
Size96 GB48 GB32 GB128 GB
Bandwidth83 GB/s60 GB/s136 GB/s120 GB/s
GPUIntel GraphicsIntel GraphicsArc 140VIntel Graphics
RTNoNoYESYES
EU / Xe96 EU2 Xe8 Xe4 Xe
Max Clock1.3 GHz2.6 GHz2 GHz2.5 GHz
NPUGNA 3.017 TOPS48 TOPS49 TOPS






PPT1.jpg
PPT2.jpg
PPT3.jpg



As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



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Guess it means fewer side-channel vulnerabilities. Also less heat generation. And less cache contention. Why pretend to have virtual cores when you can have plentiful E-cores. Interesting move. Is AMD gonna do the same?
Heat, I don't think really factors in. SMT is a significant net improvement to throughput efficiency. But the E-cores are even better in that role, and there are the side channel considerations as you mention. At the end of the day, however, this is most likely a design tradeoff/compromise. It's certainly going to hurt Cinebench scores and such.

AMD will probably spend a lot of time debating this topic over the next couple of years. I think the big question is whether this signifies a permanent shift in Intel's strategy (including for server), or if it's only a temporary move for client-only LNC.
 
Lol

Man you have to keep up. Way too much faith in Intel as if they're throwing everything on their own processes.
I acknowledge that ARL-S has a high probability of being on N3. I genuinely didn't know that was the case with LNL as well. I can't find it anywhere on the internet either.
 

Mtl igpu
I just wish intel wont Abandon i5 and i3 and gave them good igpu
 
Heat, I don't think really factors in. SMT is a significant net improvement to throughput efficiency. But the E-cores are even better in that role, and there are the side channel considerations as you mention. At the end of the day, however, this is most likely a design tradeoff/compromise. It's certainly going to hurt Cinebench scores and such.

AMD will probably spend a lot of time debating this topic over the next couple of years. I think the big question is whether this signifies a permanent shift in Intel's strategy (including for server), or if it's only a temporary move for client-only LNC.
AMD will almost certainly go in the same direction.
 
It's inherent to Lion Cove, for better or worse. ARL will have the same restrictions as Lunar Lake.
M1 doesn't have SMT either. Now I expect great results from Lunar Lake and Arrow.

Hyper threading doesn't make something automatically better.
 
If there is no SMT on Lion Cove maybe they need a 8+32 config or how could they increase MT over RPL-R? With IPC improvements only?
 
I'm sorry bro
If you don't think Arrow and Lunar both based on TSMC 3nm with uarchs based on efficiency first design and with their big cores also focusing on high ST performance then I don't what to say.

Arrow lake will be bigger than Alder lake was for desktop and same with Lunar for Ultra thin laptops. This is Intel's first time using TSMC node for CPUs and their engineers can go all out without worries of node delays.
 
Wow, I feel somewhat vindicated after being drug pretty hard a few months back for proposing that Intel would do better to make their big cores all-in for single thread throughput at the expense of SMT...
Yeah I thought that. There is a reason why ARM cores forfeit SMT it's not needed when you have ecores and SMT also has other issues.

The M series and the upcoming Nuvia chips don't have SMT has well. Maybe LNC is the start but either way it's exciting to follow the CPU industry now
 
If you don't think Arrow and Lunar both based on TSMC 3nm with uarchs based on efficiency first design and with their big cores also focusing on high ST performance then I don't what to say.
The reality is a bit different to that.
Arrow lake will be bigger than Alder lake was for desktop and same with Lunar for Ultra thin laptops
I wish it was but alas.
Lunar will be decent though.
it's not needed when you have ecores
Vulcan-derived designs had SMT and were very much ARMv8.
It's just a question of spending validation time for it.

Oh and Samsung M6 also had SMT planned in (for phones, no less).
 
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If you don't think Arrow and Lunar both based on TSMC 3nm with uarchs based on efficiency first design and with their big cores also focusing on high ST performance then I don't what to say.
Lunar Lake isn’t planned to be on N3, not at the moment at least. Arrow Lake seems likely to use N3 for desktop (unless something crazy happens), Lunar Lake is intended as a derisk product for 20A/18A.
 
Ha, Golden Pig Upgrade @ Bilibili claimed that Intel 20A is gone missing....

Arrowlake.png


It seems like Arrowlake will be fully based on TSMC's N3 node, and if anybody still believe Lunar Lake will be based on 18A, come back next year 🙄
 
No SMT on LNL makes sense coz it's an ultra low power core.

ARL lacking SMT doesn't seem plausible.
I agree. I would take this claim with a huge grain of salt. Only way this would make sense for ArL at all is if they did indeed produce an 8+32 configuration, and rumors are that configuration is cancelled or delayed.
 
I've got very good reason to think ARL doesn't have SMT either, take that for what it's worth.

Although admittedly, for the longest time I did just think it was a typo.
 
Arrow uses the same core design???
Too vague for me to tell how much he/she knows, but @adroc_thurston is certainly right that LNL is by far the more interesting of the two.
Lunar Lake isn’t planned to be on N3, not at the moment at least.
Lunar Lake is and always was on N3.
Ha, Golden Pig Upgrade @ Bilibili claimed that Intel 20A is gone missing....
As far as I'm aware, this is not true, though it's possible I'm behind the curve. I'd take that claim with quite a bit of salt, however.
 
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