Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[lakedude]

N2 never had BSPDN.

Whoops, I meant N2P...

TSMCs 2nm nodes get NanoFlex, N2P loses backside power delivery

TSMC gives an update on 2nm.

www.tomshardware.com

 

[Hitman928]

No, it's N2, then N2P then A16. For Intel it's 18A, 18A-P and then 14A.

N2P and A16 arrive within the same time frame according to TSMC.

 

[RTX]

N2P and A16 arrive within the same time frame according to TSMC.

"The roadmap you see here is pretty much the same, actually it is the same technology roadmap that I think you saw during the [technology] symposium six months ago," said Dan Kochpatcharin, Head of Design Infrastructure Management at TSMC. "[…] We have N2, N2P, which is coming [to] productions next year and the year after. And then [they are] followed by A16."
Sounds like A16 arrives after N2P.

 

[Hitman928]

"The roadmap you see here is pretty much the same, actually it is the same technology roadmap that I think you saw during the [technology] symposium six months ago," said Dan Kochpatcharin, Head of Design Infrastructure Management at TSMC. "[…] We have N2, N2P, which is coming [to] productions next year and the year after. And then [they are] followed by A16."
Sounds like A16 arrives after N2P.

Keep reading. . .

I asked TSMC's heads of the PR department to clarify. Indeed, all of these process technologies are slated to be ready for high volume manufacturing (HVM) in late 2026.

 

[Doug S]

N2P and A16 are released at the same time, or at least close enough in time that TSMC's roadmap shows them hitting mass production in H2 2026. All evidence is that A16 is identical to N2P except for the addition of BSPDN. That's just a minor variation on TSMC's original stated plans which had them release N2, then six months later follow it up with a version of N2 that added BSPDN.

I'm still operating under the belief that TSMC is working to get "back on schedule" for Apple's needs, like they were until their N3 problems caused them to go off the rails a bit.

 

[SiliconFly]

.

 

[Panino Manino]

Bringing this video here for now particular reason, other than it talks about Intel and that I don't remember even seeing this channel being mentioned here.

 

[adroc_thurston]

can Intel survive

Yes.
Question is what will survive.

 

[Hulk]

The US government will bail out Intel if need be. It's simple. A guaranteed supply of wafers is requied for defense and other mission critical applications. At the end of the day it doesn't matter if these chips are produced on an old node. As we all know, NASA was using 20 year old nodes to mitigate the effects of radiation exposure to space bound CPU's and most of them are still operational.

 

[DrMrLordX]

A guaranteed supply of wafers is requied for defense and other mission critical applications.

Okay, but is a leading-edge foundry producing consumer or even enterprise products necessary to fulfill that purpose?

 

[511]

https://twitter.com/x/status/1862051872099663931

G31 Leak

 

[moinmoin]

G31 Leak

"don’t treat it as a leak" though.

 

[LightningZ71]

Not a real leak, just dampness at the seam...

 

[Hulk]

Okay, but is a leading-edge foundry producing consumer or even enterprise products necessary to fulfill that purpose?

I don't know and that is a good question. What other US based and owned foundries are available and what how do they compare to Intel in terms of process technology and capacity?

 

[511]

I don't know and that is a good question. What other US based and owned foundries are available and what how do they compare to Intel in terms of process technology and capacity?

Answer is simple No one besides Intel not even in the US in the entire West no one outside Intel can do advanced logic and Micron for Memory

 

[maddie]

Answer is simple No one besides Intel not even in the US in the entire West no one outside Intel can do advanced logic and Micron for Memory

Does GloFlo not exist? They aren't on the cutting edge but quite adequate for defense. Things like background radioactivity, increased in (God forbid) an ultimate war, plus electromagnetic pulse effects have to be assumed. Smaller nodes are more susceptible.

 

[511]

Does GloFlo not exist? They aren't on the cutting edge but quite adequate for defense. Things like background radioactivity, increased in (God forbid) an ultimate war, plus electromagnetic pulse effects have to be assumed. Smaller nodes are more susceptible.

We need analog as well and we have TI for that Global Foundries can't even make anything below 14nm which is sufficient for most unless you require custom silicon on advanced logic do you have any other option for that also Intel has Intel 16 as well 🙂 they already signed Mediatek as a customer for that and it is based on tried and tested the exalted "14nm" do you think any process is as mature as Intel 14nm ?

If you are bringing EM Pulse/ radioactivity you to have design and fab considering it regardless of node features process are designed with this in mind

 

[igor_kavinski]

Resharing Google Lens translation of a slide posted by Flametail:



I think 258V could've won this test in battery life per watt hour too if two of the Lion Cove cores had been replaced by Skymont ones.

 

[desrever]

Resharing Google Lens translation of a slide posted by Flametail:

View attachment 112301

I think 258V could've won this test in battery life per watt hour too if two of the Lion Cove cores had been replaced by Skymont ones.

skymont isn't more efficient than lions cove tho

 

[SiliconFly]

.

 

[DrMrLordX]

I don't know and that is a good question. What other US based and owned foundries are available and what how do they compare to Intel in terms of process technology and capacity?

Does GloFlo not exist?

GlobalFoundries does exist, and they do work with the DoD:

Biden-Harris Administration Announces Preliminary Terms with GlobalFoundries to Strengthen Domestic Legacy Chip Supply for U.S. Auto and Defense Industries

U.S. Department of Commerce Outlines $1.5 Billion in Potential Funding to Support Multiple Projects in New York and Vermont and Create Approximately 10,500 Construction and Manufacturing Jobs

www.commerce.gov

 

[Meteor Late]

Until they increase the IPC of E cores by another 20% to 30%, there’s no replacing the P cores.


Totally! Intel should get rid of Skymonts asap.

I mean, Geekerwan showed how Skymont is much less efficient than Lion Cove at the upper end of the curve at the same performance. Same trend shown by Oryon M vs Oryon P.
So it's not as easy as just increasing another 30% IPC for E cores and replacing P cores. Battery life will be worse unless you worsen the user experience a lot when on battery by heavily downclocking max clock speed even in lightly threaded workloads.
What I could see, though, is reducing the number of P cores, at least on Laptops, 2 could suffice tbh if E cores are really good.

 

[desrever]

Totally! Intel should get rid of Skymonts asap.

I mean it would make their CPUs more power efficient.

 

[LightningZ71]

The 2+8 ADL p and u chips do just fine in most general use cases. 2 P cores is plenty for web browsing and light usage. It's not amazing, but, having used them for work, it's not hampering me in any way.

 

[coercitiv]

I mean, Geekerwan showed how Skymont is much less efficient than Lion Cove at the upper end of the curve at the same performance. Same trend shown by Oryon M vs Oryon P.
So it's not as easy as just increasing another 30% IPC for E cores and replacing P cores.

Falling behind at high perf levels is normal, as currently they are built with a different performance target in mind (both core layout and cache structure are aimed at PPA). You can think of this as the reverse of what happened to Zen and Zen C, when optimized for PPA the Zen core loses efficiency at high clocks (and clocks lower too). So in theory, if you wanted to make a P core out of Skymont, you would optimize the layout to ensure better voltage scaling at 4-5Ghz and give it access to proper L2/L3. The core would be bigger, use a bit more power at lower perf levels, but would scale much better at high clocks.

I think folks in the forum should talk less about replacing P cores with E cores, and more about replacing Cove with Mont (arch families). P and E are roles, and they can even be played by the same arch with some tweaks (as shown by AMD). A real world product based on the pedigree of the Mont cores would benefit from a properly planned architecture, they would have this target in mind as they plan the core. Ideally we would want a core close in size to the latest Coves, but with performance to justify the area.