Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[H433x0n]

Lets not forget all the mitigations coming for RL and RL-R to mitigate the instability issues. They will be lucky to maintain parity with Zen 4, much less Zen 5. And it looks like ARL will show little if any gain in gaming, based on the minimal single thread gains and possible increased latency due to the tiled design.

That's just not true. The Intel baseline profile in the latest Asus BIOS has no perceivable performance hit in gaming. I've been able to test it myself since I'm running it right now. Most games are using <150W of power, that's well before it bumps into any current limits if the load line is calibrated correctly.

 

[Kepler_L2]

A leak from last year referenced PL2 177W for ARL-S 8P-16E.

Intel Arrow Lake-S CPU power limits: 125W PL1, 177W PL2, 333W PL4 | igor´sLAB

Intel’s upcoming Arrow Lake-S desktop CPUs are said to be particularly efficient with power limits of 125W for the PL1, 177W for the PL2 and 333W for the short-term PL4 as the absolute upper limit for…

www.igorslab.de

Comparison had to be done @250W because that is the setting for consumer RPL. Whether ARL-S continues with the madness remains to be seen.

That's the baseline profile, where Raptor Lake has 180W power limit.

 

[AcrosTinus]

If 3% single thread improvement is true, it would be really LOL. And people were trashing 15% for Zen 5.

Even the e-cores seem really terrible based on the multithreaded score and using 250W. So much power for such a modest improvement on 3nm.

hmm...
See a leak of 15% more performance -> immediate discard.
See a leak showing the opposite, a less than 5% gain -> entertain and discuss.

At this point I'll just wait.
We get either sameish performance that is coolable or gain a nice boost that still requires the same cooling. Anything else, just skip to the next or next.next generation.

 

[H433x0n]

If 3% single thread improvement is true, it would be really LOL. And people were trashing 15% for Zen 5.

I know the ES2 estimates, the figures given were 1.03-1.07 1T performance increase over RPL refresh. Those estimates could end up being correct and the 1T performance would be competitive with Zen 5. This is an example result we have for Zen 5 against a 14900K running intel baseline profile and XMP DDR5-6400. Even if ARL-S has an anemic 1T increase, it's going to be competitive.

 

[dullard]

Oh dear, that leaked slide was optimistic. 3%/15% is even worse than 5%/20%. As to why . . . is it possible that N3B is inflicting some kind of power scaling problem? Are we going to see a situation similar to what we saw with Zen4, where power scaling past ~120W PPT didn't help performance that much?

1) The supposed 3% ST / 15% MT is an engineering sample. Even if the final silicon is unchanged, BIOS/microcode updates alone will add a percent or two of performance between now and launch. Going with a conservative 1% improvement that would lead to 4% ST / 16 % MT. Any hardware change or better code optimizations would be better than that.

2) Your memory is failing. That old Intel leak was not 5% ST / 20% MT. The leak has ST improvement of 3% to 8%, and MT improvement of 11% to 21%. So, if we take the midpoint of those ranges from the leaked slide, it predicts 5.5% ST / 16% MT. https://www.igorslab.de/wp-content/uploads/2023/07/Image-02-980x346.jpg In the end, that old Arrow Lake leaked slide was no more or no less optimistic than Jaykihn's numbers.

3) Arrow Lake is and always has been about significant iGPU and NPU (mobile) increases with minor decreases in power. We've been over this repeatedly.

 

[DavidC1]

3) Arrow Lake is and always has been about significant iGPU and NPU (mobile) increases with minor decreases in power. We've been over this repeatedly.
View attachment 102622

In Desktops, the 13900K has an anemic 32 EU iGPU. 2.4x that is still not that good, made worse by the fact it's on desktops. So great, it's improving something a lot in an area where it doesn't matter.

TBH, the more hype I see around the E-cores, the more wary I get lol.
In some ways, the E-cores seem to be just as resource hungry as many of Intel's previous cores (for similar PPC)....
A decent bit fewer ROB entries, but also a 3x3 decoder vs a 6 wide decoder, and an 8 wide dispatch rate vs 6 for RPC, and the massive backend, though ig no uOP cache too...

Most of the "massive backend" are simplified ports. Rather than having 3 ports capable of doing 8 things, they split it into 8 ports all doing a specific task.

The clustered decode also cuts complexity compared to single wide decoder, hence the approach. They are getting 9-wide decode likely similar in size to the single 6-wide one.

Gracemont is 2x3 and 17-wide backend but only less than 1/3rd the size of Golden Cove is it not?

If 3% single thread improvement is true, it would be really LOL. And people were trashing 15% for Zen 5.

Even the e-cores seem really terrible based on the multithreaded score and using 250W. So much power for such a modest improvement on 3nm.

I think this is a GREAT lesson on waiting for the final results. How many times have people flip flopped between being extremely pessimistic to extremely optimistic for both Zen 5 and Arrowlake? A single result sways the opinion of the ENTIRE forum, akin to a ripple from a small stone creating a massive Tsunami?

See a leak of 15% more performance -> immediate discard.
See a leak showing the opposite, a less than 5% gain -> entertain and discuss.

Our world runs on confidence. Nothing else really matters, even levelheadedness. So right now the confidence on Arrowlake crashed with that single leak, even though up until then it was all rose-colored glasses.

 

[DavidC1]

Intel seems to be not using an actual die shot, but overlaid a block diagram shot for Lunarlake, to hide information:

Intel Lunar Lake Technical Deep Dive - So many Revolutions in One Chip

Intel today unveiled its ambitious Lunar Lake microarchitecture, which takes the fight to the likes of the Apple M3, the Snapdragon X Elite, and more, bringing high end AI PC experiences within an ultraportable footprint, with smartphone-like battery life and availability. We have all the...

www.techpowerup.com

Look at how Lion Cove is laid out. It is exactly like that in the block diagram. Look how the three cache levels fit all into a space space at the bottom right, because it's a block diagram. Where the heck is that 2.5MB L2?!
https://elchapuzasinformatico.com/w.../Intel-Lunar-Lake-Dark-Silicon-Tile-Dummy.jpg

Real dies don't look like that neatly arranged, it is much more organic: https://www.semianalysis.com/p/meteor-lake-die-shot-and-architecture

It's a mini-block diagram shot for Lunarlake.

 

[Hulk]

Power consumption is a moving target. We must be very specific when making comparisons.

A 14900K can easily consume over 300W for a 40,000 CB R23 score. Or it can pull 175W for a 35,000 score. My old 13900K could do that without fine tuning. Just set P/E at 4.7/3.7 and you have it.

The point is the small gains obtained at the top of the v/f are costly indeed in terms of power and efficiency.

While there is no doubt Zen 4 is more efficient than Raptor Lake, the fact that people are pushing Raptor into very nonlinear parts of the v/f make it look more inefficient and power hungry than it really is.

ARL will be the same way and we most likely won't get any real, solid power/performance data until we get the parts in our grubby little hands and start testing them. Same for Zen 5. It's all wild speculation right now. Don't get me wrong, the speculation is fun, but it's also wild.

 

[lightisgood]

Yeah, M2 to M3 wasn’t great but that was N5P to N3B. Intel’s going from Intel 7 to N3B.

In 200-300W power range, Intel 7 was simply good process... wasn't it?

 

[ondma]

hmm...
See a leak of 15% more performance -> immediate discard.
See a leak showing the opposite, a less than 5% gain -> entertain and discuss.

At this point I'll just wait.
We get either sameish performance that is coolable or gain a nice boost that still requires the same cooling. Anything else, just skip to the next or next.next generation.

With a huge improvement in process tech and a new core design, couldn't we maybe, you know, have BOTH? As for skipping a generation or two, looks like at least 2 years, because the next generation is another refresh.

 

[ondma]

These overblown stability issues will be solved via profile that one can adopt or not. For 14900K to lose against vanilla zen4, nearly 15 to 20% performance has to be lost.
This will never happen.

According to Techspot 12 game average, the difference is only 10%, not 15 and certainly not 20. https://www.techspot.com/review/2749-intel-core-14th-gen-cpus/

Edit: the latest info that I could find from mid June says there is not even a final fix. The initial fix to lower the power limit was said to lower performance up to 9%.

 

[DrMrLordX]

I was thinking about chipsets.
I know that when microprocessors where "invented" they came bundled by support chips. I imagine that with time not only some of those chips were Incorporated to the processor itself, like the one to control and manage memory, but also where consolidated into one larger chip that came to be called "chipset", exactly because it was about that "set of chips" needed to make the processor work.

Is there any place out there that tells this story?

Off-topic but I'll do my best.

Once upon a time, a lot of functions we consider integral to the CPU did not actually exist in the CPU in the x86 world. Things like a memory controller or even x87 FPU were external to the CPU. They had to be connected by some form of a bus. You'd have to look at individual platforms/sockets to see exactly how they were connected.

On top of that, CPUs did not have much (or any) I/O functionality baked into the CPU. Most of what came to be known as chipsets included as much of the board I/O as possible. ISA, PCI, etc. Here's a 386DX motherboard layout:

https://alexandrugroza.ro/microelectronics/system-design/isa-80386dx-sbmc/_pict/isa-80386dx-sbmc-schematic.png

You don't see an ISA controller anywhere here (for example), so you should assume that that function has already been integrated into the chipset.

1) The supposed 3% ST / 15% MT is an engineering sample. Even if the final silicon is unchanged, BIOS/microcode updates alone will add a percent or two of performance between now and launch. Going with a conservative 1% improvement that would lead to 4% ST / 16 % MT. Any hardware change or better code optimizations would be better than that.

Doesn't seem like that would improve much.

2) Your memory is failing. That old Intel leak was not 5% ST / 20% MT. The leak has ST improvement of 3% to 8%, and MT improvement of 11% to 21%. So, if we take the midpoint of those ranges from the leaked slide, it predicts 5.5% ST / 16% MT. https://www.igorslab.de/wp-content/uploads/2023/07/Image-02-980x346.jpg In the end, that old Arrow Lake leaked slide was no more or no less optimistic than Jaykihn's numbers.

Wow, looks like I got that slide totally wrong, along with all the other people that just abstracted it to 5%/20% instead of 5.5%/16% which is . . . okay that isn't much difference. At this point it seems like you're arguing just to argue.

3) Arrow Lake is and always has been about significant iGPU and NPU (mobile) increases with minor decreases in power. We've been over this repeatedly.

Wow we must be reading differernt threads then, because all I've seen are page after page about how great Lunar Lake is going to be and why that means Arrow Lake is gonna destroy <insertcompeititonhere>.

 

[H433x0n]

If 3% single thread improvement is true, it would be really LOL. And people were trashing 15% for Zen 5.

Even the e-cores seem really terrible based on the multithreaded score and using 250W. So much power for such a modest improvement on 3nm.

If it’s terrible .. what does that say about the competition that is likely going to have nearly identical 1T and nT performance?

To me it would suggest they’re both running into similar limits.

 

[DrMrLordX]

the competition that is likely going to have nearly identical 1T and nT performance?

Huh? Does not compute.

 

[KompuKare]

You don't see an ISA controller anywhere here (for example), so you should assume that that function has already been integrated into the chipset.

AFAIR the ISA "bus" was mostly integral to the 8086 and later. At least I know that bad IDE drives used to hang the whole machine even before the BIOS and had assumed that was because there was very little by the way if a proper controller like with SCSI etc.

Wow we must be reading differernt threads then, because all I've seen are page after page about how great Lunar Lake is going to be and why that means Arrow Lake is gonna destroy <insertcompeititonhere>.

Yes, currently the hype trains for this, Zen5, and SnapDragon all seem to have vastly deflated if not derailed.

Guess we have to wait for actual reviews!

Not happy with the ES leakers still going about over 200 watts.

 

[dullard]

In Desktops, the 13900K has an anemic 32 EU iGPU. 2.4x that is still not that good, made worse by the fact it's on desktops. So great, it's improving something a lot in an area where it doesn't matter.

Last data that I saw showed that about 2/3rds of computers still have only integrated graphics. So outright saying it doesn't matter just sounds ignorant. The iGPU performance doesn't matter for just writing an email or simple office work. But, there are plenty of use cases where the iGPU performance does matter (for example, Solidworks struggles quite a lot on my work computer with an iGPU and company policy won't let me get an actual GPU even if my work computer had a slot for one).

Then there is the whole AI part where GPU performance does matter. You can ignore that use case, but I really think AI is taking off--especially in the business computer world where they usually only have iGPUs.

 

[dullard]

Doesn't seem like that would improve much.

The phrase "Doesn't seem" doesn't cut it with me. Try posting actual data instead of making up ideas and pretending they are true. Pre-launch BIOS vs post-launch BIOS often have more improvement than the meager 1% I went with. Look at these 4% to 9% changes with pre vs post launch BIOSes.
Same goes with Intel CPU launches, here is one example of BIOS updates pre-launch and post-launch

And here is Ian Cutress's quote on it:

On the performance side, the article title says it all: small performance gains. In our CPU performance tests, we are seeing an average +1.8% performance gain across all workloads

https://www.anandtech.com/show/1654...fers-small-performance-gains-on-core-i711700k
Why do you think it doesn't seem like post-launch BIOSes would improve CPU performance by my conservative 1%?

Wow, looks like I got that slide totally wrong, along with all the other people that just abstracted it to 5%/20% instead of 5.5%/16% which is . . . okay that isn't much difference. At this point it seems like you're arguing just to argue.

Here is your earlier quote "Oh dear, that leaked slide was optimistic." Why does something that you claim is "Oh dear...optimistic" suddenly become in your view "isn't much difference"? I'm arguing to point out the incongruities of your posts. If you don't care, fine. But that is why I am arguing.

Wow we must be reading differernt threads then, because all I've seen are page after page about how great Lunar Lake is going to be and why that means Arrow Lake is gonna destroy <insertcompeititonhere>.

I guess that at least I realize that Lunar Lake and Arrow Lake are different. If you can't tell the difference, why are you posting?

 

[AcrosTinus]

According to Techspot 12 game average, the difference is only 10%, not 15 and certainly not 20. https://www.techspot.com/review/2749-intel-core-14th-gen-cpus/

Edit: the latest info that I could find from mid June says there is not even a final fix. The initial fix to lower the power limit was said to lower performance up to 9%.

Why would I lower my power limit on a 420mm AIO, people can adopt these corrections from Intel IF they run into these problems. None of my machines exhibit those, so I don't care.

Furthermore I don't trust techspot and won't be using nerfed Intel benches to give Zen4 a win. More fair would be to bench unlimited and nerfed and let people decide.

Again overblown stability issues, hollow claims of degradation, where is the class action suit if it is really so wide spread... I call BS again.

 

[aigomorla]

Guys a Reminder..
In a Intel Designated Thread, you are not allowed to talk about another processor unless its a basis of comparision.

By definition of comparision, we mean you must mention Intel in the same post, why how you pulling the other processor into discussion is valid.

Like example...

AMD has a history of X, and IPC of Y, while INTEL has a history of Z and a IPC of, yet both are made of silicon.

This applies to APPLE as well.

Please keep the thread on track.


Moderator Aigo.

 

[DrMrLordX]

AFAIR the ISA "bus" was mostly integral to the 8086 and later. At least I know that bad IDE drives used to hang the whole machine even before the BIOS and had assumed that was because there was very little by the way if a proper controller like with SCSI etc.

Huh, interesting. ISA must have been a different animal in those days than the later PCI bus which was definitely handled by the chipset in its earliest iterations.

The phrase "Doesn't seem" doesn't cut it with me.

You're really splitting hairs over .5% ST and 4% MT? The "actual data" was the same leaked slide we both saw last year and some warnings form leakers showing numbers from an ES2. I'm just repeating an oft-repeated summary of that slide (yes, MANY PEOPLE QUOTED THE 5%/20% NUMBERS), and your own guesstimations are insignificantly different. Nobody gives a darn about a delta of +.5% ST and -4% MT from a summary of a slide from last year. Nobody. You're arguing just to argue, stop.

 

[Jan Olšan]

I think for Intel Sandy Bridge was the first true "SoC" that finally integrated everything.

The management controller of Sandy Bridge and following Intel CPUs actually resides in the chipset, AFAIK the processor is far from being able to boot itself without the PCH. PCH and the IME in it is actually the thing that boots first, IIRC.

 

[TwistedAndy]

It appears that Jaykihn's results, which showed a 3% ST and 15% MT increase, were obtained on the 4.7/4.0 GHz clocks:

https://twitter.com/x/status/1811123054841299020

Obviously, the retail CPUs will use higher clocks.

 

[poke01]

It appears that Jaykihn's results, which showed a 3% ST and 15% MT increase, were obtained on the 4.7/4.0 GHz clocks:

https://twitter.com/x/status/1811123054841299020

Obviously, the retail CPUs will use higher clocks.

This is much more impressive. To gain +3% ST against 13900K at 4.7GHz is great.

 

[Saylick]

I'm a little unclear on something regarding that tweet.

So the 4.7/4.0 clocks were with PL1 & PL2 = 250W? If so, do we really expect the retail clocks to be much higher? 250W is already rather high.

 

[pepeo]

So if the 4.7Ghz sample is 3% ahead of a 5.7Ghz 13900k (correct me if im wrong but i think this is the 1t boost clock of it), that would be ~25% higher ipc on a ES2 sample. Couple with with a final step and some microcodes, the ipc boost could be a little higher. If this thing can clock like raptor lake, or at least 5.7 and 4.6 like the chinese leaker said the qs were clocking, it will be considerably faster than raptor lake