Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[ondma]

Zen5 & ARL should have similar ST. And top-end X3D will be matched by ARL desktop Ultra 9 KS or equivalent. There shouldn't be much of a difference in ST.

And it's definitely a completely different ballgame in MT. ARL 8+32 is not just gonna crush top-end Zen5 X3D in MT, it's gonna be a complete bloodbath.

Unquestioned leadership in MT.

If we see it at all 8+32 will be ARL-R (refresh) at the earliest, right? I think it will be a victory of sorts if ARL can trade blows with Zen 5 in both ST and MT. The problem is that it is late to market. ARL would have been a great product if it had come out instead of RL-R. But coming out after Zen 5, it will just be a catch up, and Intel will most likely be behind again when Zen 6 comes out. So at best, in desktop, which is the only thing that interests me personally, I see Intel alternating between parity and being behind for the foreseeable future. I dont really see a scenario where they are leading in performance, unless AMD falters or there is in fact a Royal Core somewhere in the pipeline that eventually that will be a game changer.

 

[H433x0n]

Dont forget there will be a clock speed regression of 5-10% at least, and a IPC 20% seems a bit high. So final result, I would think 10% faster than RC ST would be an acceptable result. As for MT, if the E cores are as good as the predictions, there should be plenty of horsepower for a good MT performance. It will depend on temps and power usage, i.e. what clocks they can hold in full core load.

Depends on if the leaked figures for ARL-S QS silicon is correct, those figures would suggest a 5% clock regression.

If we see it at all 8+32 will be ARL-R (refresh) at the earliest, right? I think it will be a victory of sorts if ARL can trade blows with Zen 5 in both ST and MT. The problem is that is is late to market. ARL probably would have been a great product if it had come out instead of RL-R. But coming out after Zen 5, it will just be a catch up, and Intel will be behind again when Zen 6 comes out.

As of now the 8+32 SKU is dead.

 

[SiliconFly]

.

 

[H433x0n]

8+16 is more than sufficient to kill the competition in MT.

It's boring but I'd wait until 3rd party benchmarks. I personally think ARL-S will do fine in the typical reviewer 1T & nT workloads (especially if it has HT enabled).

The big question is memory latency and how it effects gaming performance. There's also the question of how well does CAMM2 memory perform compared to UDIMM memory. Apparently CAMM2 is worth +400Mts on its own over UDIMM. It's possible ARL-S has tons of memory bandwidth with poor latency and its gaming performance could be hit or miss depending on the title.

 

[Hulk]

Seems like Skymont has "legs." I am wondering how many more transistors it would need to equal or surpass Lion Cove? Seems like there is a lot of budget there to make that happen and still save die space, assuming both the big and little cores were Skymont architecture based.

I am also wondering if Lion Cove is a more general purpose architecture as compared to Skymont and there might be specific compute domains where Skymont might fall badly on its face and that is why Lion Cove must be present?

Of course there is the clock speed issue as well but that could probably be addressed in a redesign.

From an area vs. performance perspective Skymont vs. Lion Cove is reminding me of Core vs. Net Burst.

 

[trivik12]

https://twitter.com/x/status/1798324727733506249

Panther supposedly targets more segments than Lunar. So probably Tiger Lake to Lunar's Icelake kind of release.

 

[Hulk]

Well, I'm normally not a fan of on package memory, in the case of lunar lake, it's fine. They are offering either 16 or 32 GB and those are the right numbers.

 

[SiliconFly]

.

 

[dullard]

Well, I'm normally not a fan of on package memory, in the case of lunar lake, it's fine. They are offering either 16 or 32 GB and those are the right numbers.

I think of the many dozens of computers that I've worked on, I've only upgraded the memory on two of them. One needed it, the other was just for fun since I merged two ancient computers into one slightly better one. If an enthusiast like me rarely upgrades memory, regular users will do it far less often. I can see why companies make the decision for fixed memory. Plus, this ultra thin laptop / tablet / gaming device / kiosk is not the typical use case for heavy memory needs.

But, I do agree with you that at least Intel choose good quantities.

 

[trivik12]

I think we have to thank Microsoft as well as they set 16GB minimum for copilot+ PC.

 

[Khato]

Yeah, normally all Intel can do if an OEM wants to cheap out of memory is withhold a sticker. With on package memory Intel can ensure there are no 8GB single-channel monstrosities for common consumers to fall victim to.

 

[Hulk]

If ARL is indeed 8+32 (or even 24) AND Skymont=Raptor Cove ST then that will be a monster CPU for MT for client. I lean towards believing Skymont is comparable to Raptor Cove because Intel also told us Gracemont was about equal to Skylake ST. I didn't believe it then but it turned out to be true.

Gracemont equaling the outdated Skylake architecture is one thing, but Raptor Cove is Skylake after 2 major and one minor update. Raptor architecture is still formidable today whereas Skylake was far behind the times when Alder Lake was released.

Lunar Lake and Zen 5 are looking to be great parts.

 

[Hulk]

I apologize for all of my questions but what is the "memory side cache" on LL?

Also does anyone know of a place to download the entire LL slide stack?

 

[gdansk]

I apologize for all of my questions but what is the "memory side cache" on LL?

Also does anyone know of a place to download the entire LL slide stack?

A system wide cache of 8MB which is thought to be primarily used by the E core cluster (and NPU)

 

[Magio]

https://twitter.com/x/status/1798324727733506249

Panther supposedly targets more segments than Lunar. So probably Tiger Lake to Lunar's Icelake kind of release.

IIRC Panther Lake is supposed to cover the whole client side and bringing it all back to 18A (no clue how they're gonna have capacity for that, tho).

But I don't know if there'll be anything quite like LNL there, fully targeting the low power crown, with on package DRAM and all that. There should be a PTL-U, but for example the leaked Dell roadmap shows an entirely new XPS 13 SKU launching early 2026, after PTL but equipped with LNL still and only slated for a refresh when Nova Lake launches, unlike the XPS 14 and 16 which have a PTL refresh on the roadmap.

Of course things can change and that roadmap is unlikely to be fully accurate, but maybe this means PTL-U will have lower tier SKUs compared to LNL.

 

[Hulk]

Fooling around a bit with the compute die shot.

Edit - Started with the wrong area! 240mm^2! See my later post for correct numbers.

 

[Saylick]

Fooling around a bit with the compute die shot.

I thought the compute tile was 140 mm2...?

 

[Tigerick]

Some updates from my source:

• the core in ARL is slightly beefier. Beside higher clock speed, L2 cache is 3MB (vs 2.5MB on LNL). The e-core is on the Ringbus, so gets access to L3. Of course, it is still 4-tile design vs 2 tiles of LNL, memory controller is inside the SoC tile.
• Next year, Intel might not launch the 8+32 version of ARL-S. It was in the roadmap before, now no more...
• The reason might be Intel has to increase the TOPS of NPU to 40 due to Microsoft's mandate requirements. My source can't confirm which process new SoC tile is being fabbed.

It is early leaks, I will update if anything new come up.

 

[Ghostsonplanets]

The reason might be Intel has to increase the TOPS of NPU to 40 due to Microsoft's mandate requirements. My source can't confirm which process new SoC tile is being fabbed.

Can't they just use the new N4P GPU tile of Arrow Lake H to give the necessary TOPs for ARL-S Refresh next year?

The ARL H IGP tile brings back XMX while also clocking higher. Pretty sure it would be able to match the 40 TOPs requirement easily (Although the problem I think is that Desktop get a 64 XVE iGP while ARL H one is 128 XVE. So that's an area and cost increase either way).

 

[trivik12]

I thought NPU is just for laptops. I guess to call any desktop CPU as copilot plus you need one there as well. But wouldn't add on card be better for that. Its a waste of leading edge node space to use it for NPU.

 

[Ghostsonplanets]

Of course things can change and that roadmap is unlikely to be fully accurate, but maybe this means PTL-U will have lower tier SKUs compared to LNL.

PTL-U is basically Lunar Lake but for mainstream. 4P + 4LPE and Xe³ Celestial Graphics but 1/2 GPU compared to LNL Xe².

It's basically a cheaper version of LNL. So it make sense that there's no LNL successor because LNL by itself is a new swimlane and future generations will depend on the success of the product itself. If it does well, it will be iterated on. If it doesn't, it suffer the same fate as Core M.

 

[Ghostsonplanets]

I apologize for all of my questions but what is the "memory side cache" on LL?

If you're familiar with mobile phones SoC, you might have heard of Memory Side Cache as SLC (System Level Cache) or LLC (Last Level Cache).

It's basically a buffer cache structure in-between the last level of cache of the CPU and the memory dram to avoid unnecessary dram requests and reduce energy, while also providing a increase in available bandwidth.

On Lunar Lake, the CPU and NPU can make usage of it. The Xe² GPU doesn’t because by itself it has a L2 cache of 8MB.

 

[Hulk]

I find it very gutsy that Intel is using TSMC's N3B for the compute tile. When Arrow Lake or Panther Lake are released using Intel nodes we are going to have a pretty good head-to-head comparison of how these competing nodes perform on similar architecture.

Did they "have" to use TMSC for LL to make it successful because their comparable node wasn't ready, which is an outright admission they are behind in process tech? If so then they must be pretty confident in their process roadmap fulfilling performance expectations.

Bold move Intel. I like it.

 

[Hulk]

I thought the compute tile was 140 mm2...?

Yes, the compute tile includes Lion Cove, Skymont, NPU, GPU, etc..

 

[Ghostsonplanets]

Did they "have" to use TMSC for LL to make it successful because their comparable node wasn't ready

Yes. When ARL and LNL were well into development, Intel had no comparable node and was stuck on Intel 10. So they had no choice but to go to TSMC.

ARL and LNL were also greenlighted/started development when Brian and later Bob were looking at whether Intel would keep their foundry structure or revamp it/spun-off it. The allocation and first access orders to TSMC next generation N3 node was done under Bob tenure back in 2020. Hence why both use TSMC.

Pat new IDM 2.0 structure though gives freedom to their Product Teams to choose whichever node suits their product best. So we might see future Intel products using TSMC bleeding nodes still. But the pressure is there for the teams to return towards Intel Foundry manufacturing only.