Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing Raptor Lake-U. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q1 2026.

		Intel Raptor Lake U	Intel Wildcat Lake 15W?	Intel Lunar Lake		Intel Panther Lake 4+0+4
Launch Date		Q1-2024	Q2-2026	Q3-2024		Q1-2026
Model		Intel 150U	Intel Core 7	Core Ultra 7 268V		Core Ultra 7 365
Dies		2	2	2		3
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		Intel 18-A + Intel 3 + TSMC N6
CPU		2 P-core + 8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		4 P-core + 4 LP E-cores
Threads		12	6	8		8
Max Clock		5.4 GHz	?	5 GHz		4.8 GHz
L3 Cache		12 MB		12 MB		12 MB
TDP		15 - 55 W	15 W ?	17 - 37 W		25 - 55 W
Memory		128-bit LPDDR5-5200	64-bit LPDDR5	128-bit LPDDR5x-8533		128-bit LPDDR5x-7467
Size		96 GB		32 GB		128 GB
Bandwidth				136 GB/s
GPU		Intel Graphics	Intel Graphics	Arc 140V		Intel Graphics
RT		No	No	YES		YES
EU / Xe		96 EU	2 Xe	8 Xe		4 Xe
Max Clock		1.3 GHz	?	2 GHz		2.5 GHz
NPU		GNA 3.0	18 TOPS	48 TOPS		49 TOPS

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[igor_kavinski]

I often edit way after I post, so go read again. The E cores are still behind in clocks.

That is bad posting behavior. Sorry. Better to link to your original post and offer a revision of your thoughts.

 

[DavidC1]

That is bad posting behavior. Sorry. Better to link to your original post and offer a revision of your thoughts.

Then don't read it. Done.

 

[igor_kavinski]

Israel Design Center, the guys who have been doing P-core design for many years.

They have this stupid brute-force mindset because they've never had to compromise on availability of resources. It's like a bodybuilder hoarding and using up the food in the common room fridge and claiming he can pound anyone to bits and pieces and then getting his ass spanked when someone agile strategically tires him out.

 

[igor_kavinski]

My inference is that Keller made a far bigger impression with the Atom team than IDC.

Yeah adroc stated that IDC hated Keller. You need to have a humble mindset to accept and take constructive criticism and accept that maybe your ideas weren't the best.

 

[igor_kavinski]

Is there any technical limitation to it or is it artificial from Intel and mobo makers that require at least one P core active form BIOS settings to POST and boot PC to an OS.

Most likely artificial, just like disabling AVX-512 in Alder Lake. Core i3-N305 is all E-cores.

 

[Wolverine2349]

I've said it many times before that Gracemont was already at Sunny Cove/Cypress Cove-level IPC, at least for integer.

I had no doubt in my mind that the initial claims where it was said that Skymont is targeting ADL level performance would be true in the end.

For integer though for FP, wasn't Gracemont even behind Skylake by like a lot which is not good.

If Skymont really has equal or slight better FP and better Integer than Golden Cove and it can clock decently we already have a non hybrid Golden Cove based option with more than 8 cores (could maybe disable the P cores and non hybrid Skymont arch and the dream of a 10-12 P core or more Golden Cove cores like IPC chip on same die) maybe assuming they have good cache and latency levels. Though reports indicate final Skymont will be closer to Tiger Lake than Golden Cove but future Conroe moment looks promising though unlikely this Fall we even have Golden Cove IPC non hybrid good latency high clocked option unfortunately.

 

[Philste]

Link?

Beitrag im Thema 'Lunar Lake vs. Snapdragon X: Intel stört Qualcomm mit Teaser, Arrow-Lake-Details im Juni' https://www.computerbase.de/forum/t...ow-lake-details-im-juni.2196494/post-29458368
Beitrag im Thema 'Lunar Lake vs. Snapdragon X: Intel stört Qualcomm mit Teaser, Arrow-Lake-Details im Juni' https://www.computerbase.de/forum/t...ow-lake-details-im-juni.2196494/post-29458417

 

[Henry swagger]

For integer though for FP, wasn't Gracemont even behind Skylake by like a lot which is not good.

If Skymont really has equal or slight better FP and better Integer than Golden Cove and it can clock decently we already have a non hybrid Golden Cove based option with more than 8 cores (could maybe disable the P cores and non hybrid Skymont arch and the dream of a 10-12 P core or more Golden Cove cores like IPC chip on same die) maybe assuming they have good cache and latency levels. Though reports indicate final Skymont will be closer to Tiger Lake than Golden Cove but future Conroe moment looks promising though unlikely this Fall we even have Golden Cove IPC non hybrid good latency high clocked option unfortunately.

You will get 12p and 16 p cores from intel on with nova lake and beast lake

 

[jur]

Imo, there's no way Skymont has better fp than GLC. Maybe for scalar and 128 bit vector. GLC has 2x256 bit fma, new adders, 3X256bit load / cycle. Maybe it'll be close in everyday apps with limited amount of vector code. See chipsandcheese golden cove analysis; Golden cove core has huge throughput, but it's ineffective / hard to access these resources, not to mention, they disabled AVX512. Skymont seems to be designed with less raw horsepower in mind, but more effectively with improvements that affect greater amount of code base.

 

[Wolverine2349]

You will get 12p and 16 p cores from intel on with nova lake and beast lake

On the same die so no cross die severe latency penalty unlike with AMD dual CCD/CCX?

Though looks like at least 2.5 year wait for Nova Lake as late 2026 release date with vache in early 2027 per MLID.

Wish there was a more than 8 P core option much sooner or almost now with Golden Cove or better latency and IPC and clocks on same die/ring/CCD/CCX/tile/whatever.

 

[Elfear]

If the 38%/68% gains are against Crestmont:
It'll be 18% faster than Golden Cove in Integer and 6% faster in FP.

It's near Cortex X4 level, not X2.

We don't know.

Just to make sure I'm picking up what you're putting down, are you saying Skymont will be outright 18%/6% faster than Golden Cove in INT/FP or have 18%/6% better IPC?

 

[DavidC1]

Though reports indicate final Skymont will be closer to Tiger Lake than Golden Cove but future Conroe moment looks promising though unlikely this Fall we even have Golden Cove IPC non hybrid good latency high clocked option unfortunately.

Those same "reports" are basing it on the "double-digit" claim, not that the double digit might be more than 30%.

 

[Henry swagger]

On the same die so no cross die severe latency penalty unlike with AMD dual CCD/CCX?

Though looks like at least 2.5 year wait for Nova Lake as late 2026 release date with vache in early 2027 per MLID.

Wish there was a more than 8 P core option much sooner or almost now with Golden Cove or better latency and IPC and clocks on same die/ring/CCD/CCX/tile/whatever.

I think they.ll use fevoros omni on nova lake or use tsmc technology.. for better tile communication if its 16+ 32 tiles

 

[Mahboi]

Frankly with "double digit" meaning anything between 10% and 99%, I always consider it to be the worst way to present any increase.
It's basically admitting that you don't have that much.

 

[DavidC1]

Just to make sure I'm picking up what you're putting down, are you saying Skymont will be outright 18%/6% faster than Golden Cove in INT/FP or have 18%/6% better IPC?

Like the results for SpecCPU shows, Golden Cove is 23%/66% faster in Int and FP respectively.

If you take 5% for Crestmont and add 38% for Int and 68% for FP, you get my figure.

Of course for real world applications it will vary, and Spec is also a composite benchmark so some tests will do better than others. I'm talking about overall. "Outright" of course depends on the context. If they are clocked the same it should be in the ballpark I said.

Think of Nehalem vs Penryn. Nehalem is basically Penryn with a vastly improved memory and communications system. Nearly the same core, but greatly enhanced uncore.

So as a core Skymont is very competent just like Gracemont was. Darkmont-based Clearwater Forest on 18A with Foveros Direct sounds good to me.

 

[adroc_thurston]

Didn't you also say "no chance" when I said expecting 30% gains(which they beat here by a huge amount) with Skymont?

Yeah.
I know what SKT is and isn't.

 

[DavidC1]

At some point, diminishing returns will hit the E core like they do for every design. These huge gains are the product of 1) starting with a lower baseline, and 2) giving way more transistor budget to the design than before. It used to be ~4 E-cores equal the area of 1 P-core, and with Skymont it's closer to 2:1.

It's 3:1 not 2:1. It's a massacre.

Yeah.
I know what SKT is and isn't.

Why not just admit you were wrong? You were expecting 10-20% at best.

 

[DavidC1]

Israel Design Center, the guys who have been doing P-core design for many years. If Skymont is indeed +38% INT and +68% FP IPC, it's gonna end up within 10-20% IPC of Lion Cove, at less than half the area and power.

Are you sending us hints on how Lion Cove will perform?

 

[adroc_thurston]

Why not just admit you were wrong? You were expecting 10-20% at best.

I know what it is, and isn't.
Paste for Z5c.

 

[Elfear]

Like the results for SpecCPU shows, Golden Cove is 23%/66% faster in Int and FP respectively.

If you take 5% for Crestmont and add 38% for Int and 68% for FP, you get my figure.

Of course for real world applications it will vary, and Spec is also a composite benchmark so some tests will do better than others. I'm talking about overall. "Outright" of course depends on the context. If they are clocked the same it should be in the ballpark I said.

Okay, so you're saying the average IPC will be 18%/6% better. That makes sense. I was trying to wrap my mind around Arrow Lake e-cores being that much faster than Alder Lake P-cores.😯

I mean it does depend on Skymont clocks but I can't imagine they'll be that close to the P-cores.

 

[igor_kavinski]

Skymont may well be a good architecture but being on tile might be what doesn't let it perform to its fullest.

 

[adroc_thurston]

Skymont may well be a good architecture but being on tile might be what doesn't let it perform to its fullest.

LNL is a monodie.

 

[DavidC1]

Bonnell/Saltwell: 1x, 2-wide
Silvermont: 1.5x, 2-wide
Goldmont: 2x, 3-wide
Goldmont Plus: 2.7x, 3-wide
Tremont: 3.6x, 6-wide
Gracemont: 4.7x, 6-wide
Skymont: 6.5x, 9-wide

If this continues, the Arctic Wolf should be 8.5x, 12-wide. With another 30% gain they'll have to seriously think of doing a drastic change of the P cores.

Also: https://www.techpowerup.com/317317/...res-show-ipc-regression-over-raptor-lake?cp=3

With another 30%, Apple M3 is next. Considering where it started from, it's really good.

 

[igor_kavinski]

LNL is a monodie.

Then there's hope.

 

[ondma]

Okay, so you're saying the average IPC will be 18%/6% better. That makes sense. I was trying to wrap my mind around Arrow Lake e-cores being that much faster than Alder Lake P-cores.😯

I mean it does depend on Skymont clocks but I can't imagine they'll be that close to the P-cores.

Keep in mind though, even if the IPC figures are correct (I still find them hard to believe), Skymont will have a lower frequency as well as lacking hyperthreading, so the performance will be quite a bit lower. If SKM really is as good as the rumors indicate though, that should help mitigate the lack of HT in the P cores.