Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[H433x0n]

Intel told investors that Intel's pre-EUV nodes are very expensive and also said transition to EUV nodes will bring cost savings.

So unless Intel is BSing in an investor call, it would imply that Intel 7 yields are not good.

That’s not what that means. You can have a node with low defect density and also be expensive. If you’re doing a ton of multi patterning the throughput is lower.

 

[Joe NYC]

That’s not what that means. You can have a node with low defect density and also be expensive. If you’re doing a ton of multi patterning the throughput is lower.

If the throughput is cut dramatically, then the process is not "yielding insanely good", as the original poster asserted.

If the number of dies coming out is cut in half due to low throughput, it is not much different from dies coming out cut in half due to defects.

 

[Mahboi]

If the throughput is cut dramatically, then the process is not "yielding insanely good", as the original poster asserted.

If the number of dies coming out is cut in half due to low throughput, it is not much different from dies coming out cut in half due to defects.

So "yield" is supposed to mean yield/day or yield/month, not yield/wafer?

 

[Saylick]

C&C posted an article on Skymont, which has some interesting technical discussion. Enjoy!

Thoughts on Skymont Slides

Recently a set of Skymont slides were published, apparently without any embargo or confidentiality marks.

chipsandcheese.com

 

[poke01]

C&C posted an article on Skymont, which has some interesting technical discussion. Enjoy!

Thoughts on Skymont Slides

Recently a set of Skymont slides were published, apparently without any embargo or confidentiality marks.

chipsandcheese.com

Pretty good. It’s what Intel’s E core needed and further secured that hybrid computing is the future.

 

[Saylick]

Pretty good. It’s what Intel’s E core needed and further secured that hybrid computing is the future.

Might not even be hybrid if the rumors are true in that Intel will use all E cores that can combine into a pseudo-big core via "Rentable Units".

 

[poke01]

Might not even be hybrid if the rumors are true in that Intel will use all E cores that can combine into a pseudo-big core via "Rentable Units".

That’s not any time soon and if it’s happening it’s a big gamble to make.

 

[Thunder 57]

Might not even be hybrid if the rumors are true in that Intel will use all E cores that can combine into a pseudo-big core via "Rentable Units".

Ah yes, "reverse-hyperthreading" returns again. It doesn't work that way.

 

[Wolverine2349]

Might not even be hybrid if the rumors are true in that Intel will use all E cores that can combine into a pseudo-big core via "Rentable Units".

Well its still hybrid no matter how good the cores are if the types of so called e-cores are if they are different arch than P cores.

Technically even Zen C cores are hybrid as well as non 3D cache vs 3d cache 7900X3D and 7950X3D.

I mean a non hybrid CPU I think all cores are exactly the same including cache levels like AMD 7800X3D, 7700X, Intel Core i5-12400 (6 + 0 die), Intel 11th and 10th Gen CPUs etc... .

So if rumors are true that Intel can actually combine e-cores into a big core, would that make them exactly the same as Lion Cove? Or are you thinking more like AMD Zen 4C and 5C cores which kind of is not hybrid though it kind of is as cache level is different despite same so called IPC which seems hybrid like to me.

 

[Kepler_L2]

C&C posted an article on Skymont, which has some interesting technical discussion. Enjoy!

Thoughts on Skymont Slides

Recently a set of Skymont slides were published, apparently without any embargo or confidentiality marks.

chipsandcheese.com

IDC in absolute shambles. Almost guaranteed we get Conroe 2.0 in a few years.

 

[Joe NYC]

So "yield" is supposed to mean yield/day or yield/month, not yield/wafer?

It's another measure - processed wafers per time period.

 

[Wolverine2349]

IDC in absolute shambles. Almost guaranteed we get Conroe 2.0 in a few years.

What is IDC?

And saying we get Conroe 2.0 in a few years.

Almost makes sense. I mean after all Intel had the Pentium M mobile which was strong and they turned that into Conroe which knocked out AMD.

So are you saying you see a similar thing happening where the e-cores are used as the basis for building blocks to something bigger and better and an all P core super powered and low power chip in a few years aka Conroe 2.0?

Like Intel did with mobile Pentium M and morphed it into Conroe in 2.5 years form early 2004 to mid 2006?

 

[Kepler_L2]

What is IDC?

And saying we get Conroe 2.0 in a few years.

Almost makes sense. I mean after all Intel had the Pentium M mobile which was strong and they turned that into Conroe which knocked out AMD.

So are you saying you see a similar thing happening where the e-cores are used as the basis for building blocks to something bigger and better and an all P core super powered and low power chip in a few years aka Conroe 2.0?

Like Intel did with mobile Pentium M and morphed it into Conroe in 2.5 years form early 2004 to mid 2006?

Israel Design Center, the guys who have been doing P-core design for many years. If Skymont is indeed +38% INT and +68% FP IPC, it's gonna end up within 10-20% IPC of Lion Cove, at less than half the area and power.

There is no point in continuing with P-cores if they can just scale up E-cores with better caches/higher frequency.

 

[gdansk]

But how much more area and power would a "top end" -mont core need to displace the P cores? It would also enter the diminishing returns.

But lately the monts have been the promising bit.

 

[Hulk]

So Gracemont not close to Skylake performance.

Also was asking about supposed Skymont Arrow Lake e-cores compared to Golden Cove. Will those have the IPC and latency and core to core communication of Golden Cove? Or not even close?

I did a lot of Gracemont vs Skylake testing in Cinebench R23 a few years ago. I concluded that in ST performance Skylake had 7% better throughput (iso frequency) vs Gracemont. When Skylake is permitted to run at max frequency that lead of course increases. That's just 1 application though.

 

[Hulk]

Israel Design Center, the guys who have been doing P-core design for many years. If Skymont is indeed +38% INT and +68% FP IPC, it's gonna end up within 10-20% IPC of Lion Cove, at less than half the area and power.

There is no point in continuing with P-cores if they can just scale up E-cores with better caches/higher frequency.

Those increases seem astronomical. I hope they aren't.

 

[Geddagod]

Israel Design Center, the guys who have been doing P-core design for many years. If Skymont is indeed +38% INT and +68% FP IPC, it's gonna end up within 10-20% IPC of Lion Cove, at less than half the area and power.

There is no point in continuing with P-cores if they can just scale up E-cores with better caches/higher frequency.

I genuinely want to see SKM allowed higher area.
Even with the same node, or even same lib, one can see decent gains in speed by relaxing area constraints

I still don't think it would beat LNC either way... but I wanna see if it comes relatively close lol
But alas we still don't know SKM Fmax either...

 

[Wolverine2349]

Those increases seem astronomical. I hope they aren't.

Why do you hope they are not astronomical increases in performance?

 

[Wolverine2349]

Israel Design Center, the guys who have been doing P-core design for many years. If Skymont is indeed +38% INT and +68% FP IPC, it's gonna end up within 10-20% IPC of Lion Cove, at less than half the area and power.

There is no point in continuing with P-cores if they can just scale up E-cores with better caches/higher frequency.

Basically in that case the e-cores would become new P cores taking much less power and die size and maybe hybrid arch gone and the new P cores the only cores in CPUs in future for Conroe moment. Would love that to ditch hybrid arch and better compatibility and ease of scheduling.

Ironic that Israel Design Center whom someone mentioned designed Core 2 series years ago which was one in a kind is in shambles and cannot increase IPC or it even regresses much if at all on P cores while they still use high power on new node?

Where as the e-core team is potentially increasing IPC dramatically.

Is history repeating itself but different teams this time. Like the Netburst team in shambles 20 years ago trying to increase clocks without increasing IPC and heat consumption through roof where as the weaker lower clocked Pentium M less die size and the basis for what became Conroe. The e-cores today to what Pentium M was 20 years ago could be the modern Conroe moment and I always wondered that myself.

 

[branch_suggestion]

My inference is that Keller made a far bigger impression with the Atom team than IDC.

 

[tamz_msc]

The third and fourth slides seem to indicate single-threaded and multi-threaded perf-power curves respectively.

In ST, Skymont can have 1.7x higher performance vs. Crestmont at iso-power, or 1/3rd power at iso-perf.

In MT, Skymont can have 2.9x higher performance vs. Crestmont at iso-power, or 1/3rd power at iso-perf.

Note that the comparisons are being made at the maximum power scaling point of Crestmont, meaning that relative performance of Skymont vs Crestmont would be even higher at very low power.

 

[gdansk]

My inference is that Keller made a far bigger impression with the Atom team than IDC.

Or does Intel's backup team always save the day?
iAPX 432 vs 186/286
Itanium vs Xeon
Pentium 4 vs Pentium M/Core
Lion Cove vs Skymont?

The weird thing is now there is no backup since both cores appear in most products.

 

[Kepler_L2]

The third and fourth slides seem to indicate single-threaded and multi-threaded perf-power curves respectively.

In ST, Skymont can have 1.7x higher performance vs. Crestmont at iso-power, or 1/3rd power at iso-perf.

In MT, Skymont can have 2.9x higher performance vs. Crestmont at iso-power, or 1/3rd power at iso-perf.

Note that the comparisons are being made at the maximum power scaling point of Crestmont, meaning that relative performance of Skymont vs Crestmont would be even higher at very low power.

View attachment 100070

View attachment 100071

For the MT comparison it's 4x Skymont in LNL vs 2x Crestmont LP in MTL.

 

[Saylick]

Israel Design Center, the guys who have been doing P-core design for many years. If Skymont is indeed +38% INT and +68% FP IPC, it's gonna end up within 10-20% IPC of Lion Cove, at less than half the area and power.

There is no point in continuing with P-cores if they can just scale up E-cores with better caches/higher frequency.

At some point, diminishing returns will hit the E core like they do for every design. These huge gains are the product of 1) starting with a lower baseline, and 2) giving way more transistor budget to the design than before. It used to be ~4 E-cores equal the area of 1 P-core, and with Skymont it's closer to 2:1. While I don't doubt they could probably scale up the E core's performance if they were given the P core's transistor budget, they won't get 2x the performance. If I recall correctly, a rule of thumb for ST performance is that it's roughly proportional to the square root of the transistor budget, so with 2x the transistors a core should have ~40% higher ST performance.

 

[Hulk]

Why do you hope they are not astronomical increases in performance?

Sorry, bad writing on my part. I meant to convey that I hope the increases aren't actually astronomical from the point of view that they are realistic and attainable.