Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing Raptor Lake-U. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q1 2026.

		Intel Raptor Lake U	Intel Wildcat Lake 15W?	Intel Lunar Lake		Intel Panther Lake 4+0+4
Launch Date		Q1-2024	Q2-2026	Q3-2024		Q1-2026
Model		Intel 150U	Intel Core 7	Core Ultra 7 268V		Core Ultra 7 365
Dies		2	2	2		3
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		Intel 18-A + Intel 3 + TSMC N6
CPU		2 P-core + 8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		4 P-core + 4 LP E-cores
Threads		12	6	8		8
Max Clock		5.4 GHz	?	5 GHz		4.8 GHz
L3 Cache		12 MB		12 MB		12 MB
TDP		15 - 55 W	15 W ?	17 - 37 W		25 - 55 W
Memory		128-bit LPDDR5-5200	64-bit LPDDR5	128-bit LPDDR5x-8533		128-bit LPDDR5x-7467
Size		96 GB		32 GB		128 GB
Bandwidth				136 GB/s
GPU		Intel Graphics	Intel Graphics	Arc 140V		Intel Graphics
RT		No	No	YES		YES
EU / Xe		96 EU	2 Xe	8 Xe		4 Xe
Max Clock		1.3 GHz	?	2 GHz		2.5 GHz
NPU		GNA 3.0	18 TOPS	48 TOPS		49 TOPS

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[adroc_thurston]

LNL also scales upto 30W I believe?

You can juice more if you want.
The intended design power is the thing I'm talking about and 8cx g4 is higher than LNL in that.

Isn't Skymont targeting Golden Cove level of performance?

no.
SNC-ish.

 

[Hulk]

Isn't Skymont targeting Golden Cove level of performance?

Hardly average performing if that is indeed the case.

That' would require a 47% IPC increase.

 

[tamz_msc]

no.
SNC-ish.

I should have been more clear. Assuming perfect scaling with frequency, Gracemont in Alder Lake already matches the performance performance clock of Rocket Lake. Gracemont in Raptor Lake should be low-single digit percentage higher perf per clock than Gracemont in Alder Lake owing to the doubled L2$ per cluster.

It's not big deal for Skymont to match the perf per clock of Golden Cove.

I'm taking the figures from Andrei's testing of SPECint_rate_2017 1T.

 

[Henry swagger]

That' would require a 47% IPC increase.

Skymont will be 8wide like apple cores

 

[Markfw]

Skymont will be 8wide like apple cores

And pigs will fly.....

 

[Goop_reformed]

New performance leaks for arrow lake just drops, MLID as usual:

Arrow lake = Meteor Lake + 25-35% ( performance )

Discuss

 

[poke01]

I’m as you guys know am very excited for Arrow lake because Intel is finally will be using leading nodes late this year and early next year.

Bring on the Arrows⬇️⬆️➡️⬅️

 

[adroc_thurston]

Bring on the Arrows⬇️⬆️➡️⬅️

 

[Henry swagger]

New performance leaks for arrow lake just drops, MLID as usual:

Arrow lake = Meteor Lake + 25-35% ( performance )

Discuss

Interesting 35+ better with no smt.. taking the apple route 😏

 

[naukkis]

Except for all those workloads that have high latency but also need lots of brawn like relational DB's or generally anything in the server space that is dealing with I/O.

I cant wait for 1000's of terribly performing kubernetes containers running on 1000's of average performing core. But im cloud scale!!!!! 2024 IT is lit.

Intel big cores are just wasted in their server grade cpu's - they are enormous as they are designed to run 6GHz and they are clocked about 3Ghz in their big configurations. Running them at 3GHz with HT means that their single-thread performance is actually lower than their small-core rivals. Even Intel own E-core based solution might actually have better single-thread performance in high utilization situations than their big-core solutions - Intel is sure doomed if they don't change their mindset of designing cores that their customers actually need. Their big-core with HT solution ain't competitive in most of designs they try to sell.

 

[adroc_thurston]

Intel big cores are just wasted in their server grade cpu's

No.
They're just not particularly area/power efficient which is an overarching IDC problem and not really unique to server.

they are enormous as they are designed to run 6GHz and they are clocked about 3Ghz in their big configurations.

Yeah about that.

Even Intel own E-core based solution might actually have better single-thread performance in high utilization situations than their big-core solutions

God no, Atom caches are pretty dog, that L2 in particular is slow and tiny.

 

[naukkis]

God no, Atom caches are pretty dog, that L2 in particular is slow and tiny.

That's absolutely not core's fault. Intel does pack them that way for being easily add 4-core complexes to existing ring/mesh networks but nothing is in their way to implement different L2-cache versions. They could for example made 60-core e-core solution which have fast 12MB L2 per core in size of their Golden-cove solutions and after that there probably could be quite different performance profiles - Intel solutions might actually be competitive with other vendors.

 

[adroc_thurston]

Intel does pack them that way for being easily add 4-core complexes to existing ring/mesh networks

No, Atom cache is just made to be slow and low power (ish).

They could for example made 60-core e-core solution which have fast 12MB L2 per core in size of their Golden-cove solutions

I don't think we're going back to Penryn but I digress.
You're overthinking Atom capabilities hard.

 

[naukkis]

No, Atom cache is just made to be slow and low power (ish).

I don't think we're going back to Penryn but I digress.
You're overthinking Atom capabilities hard.

Yeah, Intel should probably just made GoldenCove much bigger and run 40 of them @2Ghz with at least 4-way SMT to be competitive with rival's smaller cores. With such a strategy they are soon out of business. Actually they already are - have to wonder which parties are actually buying their rapid-solutions as they basically aren't competitive in any workloads - either for cost, energy-efficiency or packing density - Intel probably just gives them away to give a appearance that they are still in business.

 

[Joe NYC]

New performance leaks for arrow lake just drops, MLID as usual:

Arrow lake = Meteor Lake + 25-35% ( performance )

Discuss

ST? MT? If MT, then comparing what to what?

I don't buy ST improvement of 25-35% at all.

On MT, higher number of cores (8+16 or 8+32) combined with higher power limit than MTL will result in higher MT performance. 25%-35% may be within realm of possibilities of trivially parallel workload.

 

[tamz_msc]

No, Atom cache is just made to be slow and low power (ish).

I don't think we're going back to Penryn but I digress.
You're overthinking Atom capabilities hard.

You are underplaying the capabilities that Intel has when it comes to architecture of the building blocks in terms of their granularity.

Intel can decide which core to put in a mesh building block , and route them with their corresponding MCs and other cores at the individual core level.



There is no architecture-specific restriction on the size of the L2 in this approach.

 

[SiliconFly]

.

 

[Goop_reformed]

No.
They're just not particularly area/power efficient which is an overarching IDC problem and not really unique to server.

Yeah about that.

God no, Atom caches are pretty dog, that L2 in particular is slow and tiny.

Alright, who will win Zen 5 or Arrow Lake?

ST? MT? If MT, then comparing what to what?

I don't buy ST improvement of 25-35% at all.

On MT, higher number of cores (8+16 or 8+32) combined with higher power limit than MTL will result in higher MT performance. 25%-35% may be within realm of possibilities of trivially parallel workload.

It's literally what he said in video and in the slides. No infos about st or nt

 

[SiliconFly]

.

 

[Joe NYC]

It's literally what he said in video and in the slides. No infos about st or nt

I wasn't questioning you, I was addressing the claim in the video.

 

[SiliconFly]

.

 

[SiliconFly]

.

 

[moinmoin]

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Report: Intel has quietly bought chip startup Soft Machines for $250M - SiliconANGLE

Report: Intel has quietly bought chip startup Soft Machines for $250M - SiliconANGLE

siliconangle.com

Probably something similar to this. We called it "reverse Hyperthreading".

Oh ok, it's that old stuff we already talked about in like a dozen threads over the decade. Thanks. Would be nice to see it being realized at some point, but seeing how it reliably appears and disappears again and again the chances are slim.

Skylake may feature "inverse hyperthreading"?

http://wccftech.com/intel-inverse-hyper-threading-skylake/ The concept here is sort of like VISC, taking multiple cores and getting them to appear as a single one, the opposite of what hyperthreading does, so that each core can work on the same software thread. The following...

forums.anandtech.com

 

[Hulk]

He's just shooting in the dark. He's being purposefully fuzzy just to cover his back if his prediction fails. Even if ARL performance falls out of his predicted range, he'll just introduce new elements like clocks, interconnect, packaging, cache performance, etc, to justify his claims and still say he was right. We just need to take this with a bucket of salt.

Exactly, this is pure BS. The only information provide in this "leak" is 25 to 35% performance uplift over Meteor Lake.

First, he doesn't specify clocks so we have to assume this is Meteor Lake mobile clocks compared to Arrow Lake desktop clocks and mobile memory subsystem to desktop! We know this is HUGE. That could be +20% right there is terms of performance uplift with NO architectural changes, just faster desktop memory and CPU frequency, which of course is normal for even the same generation of CPU.

Second, he's comparing tiled to tiled so no tile penalty in this comparison.

Unfortunately he made a 22 minute video that tells us absolutely nothing.

All of the obstacles I've documented Intel has with besting Raptor Lake performance, tile latency, 6+GHz Intel 7 frequencies, lack of HT for MT performance, are still there with no idea of how they will be mitigated.

At the end of the day you can buy a 14900KS next week and with good cooling get 5.9GHz all-core and 6.2GHz dual core performance right now. My curiosity remains as to how Intel accomplishes the magic act of surpassing the raw performance of that CPU?

If Arrow Lake is actually 8+16 I stand with my prediction that is will have ~15% better IPC for 5 to 10% better overall ST performance and will at best tie Raptor MT performance in well-threaded applications. I will also add that if this is the case and it is more efficient, easier to cool than Raptor Lake then this is a "better" part than Raptor Lake, but the numbers will be less impressive than actual day-to-day use mainly due to the fact that many apps still rely heavily on ST performance, and any decent air cooler will be sufficient.

 

[FlameTail]

He's just shooting in the dark. He's being purposefully fuzzy just to cover his back if his prediction fails. Even if ARL performance falls out of his predicted range, he'll just introduce new elements like clocks, interconnect, packaging, cache performance, etc, to justify his claims and still say he was right. We just need to take this with a bucket of salt.

MLID viewers must be having extreme chronic high blood blood pressure due to all the salt they take...