Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing Raptor Lake-U. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q1 2026.

		Intel Raptor Lake U	Intel Wildcat Lake 15W?	Intel Lunar Lake		Intel Panther Lake 4+0+4
Launch Date		Q1-2024	Q2-2026	Q3-2024		Q1-2026
Model		Intel 150U	Intel Core 7	Core Ultra 7 268V		Core Ultra 7 365
Dies		2	2	2		3
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		Intel 18-A + Intel 3 + TSMC N6
CPU		2 P-core + 8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		4 P-core + 4 LP E-cores
Threads		12	6	8		8
Max Clock		5.4 GHz	?	5 GHz		4.8 GHz
L3 Cache		12 MB		12 MB		12 MB
TDP		15 - 55 W	15 W ?	17 - 37 W		25 - 55 W
Memory		128-bit LPDDR5-5200	64-bit LPDDR5	128-bit LPDDR5x-8533		128-bit LPDDR5x-7467
Size		96 GB		32 GB		128 GB
Bandwidth				136 GB/s
GPU		Intel Graphics	Intel Graphics	Arc 140V		Intel Graphics
RT		No	No	YES		YES
EU / Xe		96 EU	2 Xe	8 Xe		4 Xe
Max Clock		1.3 GHz	?	2 GHz		2.5 GHz
NPU		GNA 3.0	18 TOPS	48 TOPS		49 TOPS

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[moinmoin]

Which is why consumer ARM cores don't have have multithreading.

More like ARM first went to more cores whereas x86 first added SMT. Since most ARM SoCs already had plenty cores by contemporary standards lacking SMT no longer was a pressing issue.

 

[Henry swagger]

I tend toward believing the Mercury Research market share numbers rather than any individual retailer - https://www.tomshardware.com/pc-com...new-mercury-research-data-shares-q4-2023-data

Simple fact is that Intel knows how to sell its processors on the client side as evidenced by their revenue share being higher than their unit share. Consumer marketing/brand recognition combined with supporting OEM designs goes a long way in selling products. Being notably ahead on the technical merits of the product is primarily helping AMD on the large scale server deployments.

Plus intel has a more trusted and known brand with quality

 

[Hulk]

I am disappointed at the lack of hyperthreading or increased E cores, but considering all the E cores in 14900k I doubt that HT adds 20% to overall performance.

You are right, it's 15% in CB. Still significant.
The increase in the P cores is 30% (in CB) due to HT. 389 pts/GHz to 512 pts/GHz, but that is of course mitigated in the overall scores due to the non-HT E cores. Still 15% right off the bat just to break even is a lot, plus they have to make up for the decrease in frequency AND tile latency.

That's about 20%. Let's say they get +20% from Raptor Cove to Lion Cove, which I think is a lot, and Skymont makes up 10% of the MT deficit. We could see 10% improvement from Lion Cove. Except for the fact that they could be losing 10% in frequency! Every time I do the math on this it just seems really tough for Intel to beat Raptor Lake at the top of the stack.

The MT problem is even more severe down the stack where the ratio of P to E cores increases.

 

[Hulk]

Which is why consumer ARM cores don't have have multithreading.

Problem is Intel has done a lot of "hat hanging" on CB MT.

 

[Hulk]

When Intel already has 10 cores in their lowest i5 SKU, the lack of HT in ARL will be more of a spreadsheet problem than a consumer problem. The only thing they need to do is increase core count for Ultra 3 or whatever they'll call it (the current i3).

Without even looking for actual measurements, with the conventional wisdom of "1P=2E" and "SMT=20-25%" we should be looking at a 10-12% loss in MT due to removal of SMT... and that's in Cinememe scores since for actual workloads SMT thread should be the last in the queue and most consumer workloads simply won't scale beyond the E core spam.

All we really need from ARL is stronger ST perf and minimized latency tradeoffs due to tiled structure.

Good estimates. Using my CB data with an 8+16 part they are looking at having to make up 15% for MT in the worst case Cinebench "ridiculously multi-threaded scenario.

Of course the issue is exacerbated with parts down the stack where the P to E core ratio increases.

 

[SiliconFly]

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[Hulk]

Since it's a bit more than a 2X node jump for LNC, it's gonna get a huge transistor budget due to the massive density increase which should easily compensate for the loss in Fmax. The same way Apple & Zen get additional performance when they move to a newer node. Similarly, LNC should get a lot of IPC increase too. How much increase is hard to say until they reveal the architecture, ES, etc.

How much of a transistor density increase do you think we're talking about going from Intel 7 to the TMSC node?

 

[Hulk]

I created a little ARL calculator in Excel. Red font are my guesses, blue font is calculated from guesses, and black font is known.
Based on this input data I'm seeing ARL needing 20% Lion Cove IPC improvement and 22% Skymont IPC improvement to equal the 14900K in MT. Of course in ST this ARL model beats Raptor Cove easily.

If you have a prediction give me your numbers and I will run them. All I need is your Lion Cove/Skymont IPC improvement percent, and ST and MT frequencies for P cores, and frequency for E cores.

 

[SiliconFly]

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[SiliconFly]

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[Hulk]

You haven't factored in additional ST performance due to removal of HT. I'm just taking a wild guess here... but I think it should be well above 10%.

Additional transistor budget should bring in at least 5% or more.

LNC architectural improvements should be at least double digits hopefully, which should be at least 10% or more.

Just wild guesses, but shouldn't be too off from the final product I think.

All architectural improvements are "built in" to the ST performance IPC improvement percentage.

So what are you thinking ST improvement from Raptor Cove to Lion Cove? I am estimating 20%. Are you thinking 30%? We have not seen the likes of that type of improvement since P4 to Conroe. I'm not saying it's not possible, just wondering where you put the number?

At the end of the day all iso-frequency improvements come primarily from architectural improvements, especially when the memory subsystem remains the same between generations or the new generation doesn't leverage some new instruction(s) only used for some specific software.

Lion Cove and Skymont vs. Raptor Cove and Gracemont at iso-frequency in CB R23, how much improvement? This is really what it comes down to. We can estimate release clocks pretty well.

You are also right when it comes to transitioning the HT structures to improve ST performance. I think much of that will go into better OoO logic and cache structures.

 

[AMDK11]

Following the lead of SunnyCove and GoldenCove, the expansion of LionCove logic is at least 30-40%. I don't expect any smaller expansion. Of course, the more the better.

 

[igor_kavinski]

Intel's Computex 2024 keynote to include next-gen client product showcase, Arrow Lake incoming? - VideoCardz.com

Intel CEO Pat Gelsinger to deliver Computex 2024 keynote Pat Gelsinger is now confirmed to keynote at Computex 2024 on June 4th. According to the press release, Intel will showcase its next-generation data-center and client products. For the client segment, Intel is expected to deliver updates...

videocardz.com

Imagine Lisa blowing away the crowd with pre-shipping silicon benchmarks of Zen 5 and then Pat follows that up with...gaming chips with AI!!!!

Yeah, that's just what the world needs, Pat.

 

[SiliconFly]

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[Hulk]

Following the lead of SunnyCove and GoldenCove, the expansion of LionCove logic is at least 30-40%. I don't expect any smaller expansion. Of course, the more the better.

So are you hoping for something like this?

 

[SiliconFly]

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[Henry swagger]

So are you hoping for something like this?

5.5ghz on intel 20A is to high.. mayb 5ghz

 

[igor_kavinski]

5.5ghz on intel 20A is to high

Intel's trusted brand and quality make anything possible!

 

[igor_kavinski]

So are you hoping for something like this?

That sheet really drives home the uphill struggle Intel is facing. Seems impossible. It'll be a red letter day for them if that comes true.

 

[AMDK11]

So are you hoping for something like this?

I think that looking at the average of the IPC growth curve of SunnyCove +18% and GoldenCove +19%, LionCove +20% is at least a 30-40% expansion of the core logic. If the expansion is larger than before, for example 40-50+% more, the average of the IPC curve will be higher. Anything less than 18-20% IPC increase will be a failure due to the fact that LionCove is not for one generation, but at least 2.

 

[igor_kavinski]

Anything less than 18-20% IPC increase will be a failure due to the fact that LionCove is not for one generation, but at least 2.

Has Intel stated that as a fact? I thought ARL would be followed up by Panther Lake, not a refresh of ARL.

 

[FlameTail]

Has Intel stated that as a fact? I thought ARL would be followed up by Panther Lake, not a refresh of ARL.

MLID has said the 8P+32E version is for ARL refresh.

That lines up with the rumours from other sources too.

 

[AMDK11]

Has Intel stated that as a fact? I thought ARL would be followed up by Panther Lake, not a refresh of ARL.

Don't believe that the second generation after ArrowLake will be anything other than something like RaptorLake compared to AlderLake, i.e. GoldenCove with L2 2MB instead of 1.25MB. Intel doesn't have to confirm anything here because these are historical facts. If they provide an improved microarchitecture or a completely new one compared to LionCove, it will be a very big surprise.

I sincerely doubt that the second generation after ArrowLake will not be something like RaptorLake with GoldenCove L2 2MB instead of 1.25MB and more cores due to the design time that takes a lot of time.

If the ArrowLake refresh from PantherLake is new Cove cores, the changes in LionCove are smaller than in SunnyCove and GoldenCove. This is my current position on this topic.

 

[igor_kavinski]

MLID has said the 8P+32E version is for ARL refresh.

Imagine if AMD counters that with 8 core Zen5+16 core Zen5c WITH HT...

 

[SiliconFly]

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