Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

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Tigerick

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Wildcat Lake (WCL) Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing Raptor Lake-U. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q1 2026.

Intel Raptor Lake UIntel Wildcat Lake 15W?Intel Lunar LakeIntel Panther Lake 4+0+4
Launch DateQ1-2024Q2-2026Q3-2024Q1-2026
ModelIntel 150UIntel Core 7Core Ultra 7 268VCore Ultra 7 365
Dies2223
NodeIntel 7 + ?Intel 18-A + TSMC N6TSMC N3B + N6Intel 18-A + Intel 3 + TSMC N6
CPU2 P-core + 8 E-cores2 P-core + 4 LP E-cores4 P-core + 4 LP E-cores4 P-core + 4 LP E-cores
Threads12688
Max Clock5.4 GHz?5 GHz4.8 GHz
L3 Cache12 MB12 MB12 MB
TDP15 - 55 W15 W ?17 - 37 W25 - 55 W
Memory128-bit LPDDR5-520064-bit LPDDR5128-bit LPDDR5x-8533128-bit LPDDR5x-7467
Size96 GB32 GB128 GB
Bandwidth136 GB/s
GPUIntel GraphicsIntel GraphicsArc 140VIntel Graphics
RTNoNoYESYES
EU / Xe96 EU2 Xe8 Xe4 Xe
Max Clock1.3 GHz?2 GHz2.5 GHz
NPUGNA 3.018 TOPS48 TOPS49 TOPS






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As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



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itsmydamnation

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HT is useless these days. Especially when we have so many physical cores. HT comes into play *only* when all the cores are running full steam. Otherwise, it remains idle.

The scheduler (OS/Thread Director) activates HT to quickly preempt a already running thread when a physical core is no longer available. Even if a single core is available, HT remains idle. Now that we have so many cores, HT never comes into play.

In short, HT is useful mainly for running benchmarks and running massive multitasking loads like video encoding. Otherwise, it's pretty much waste of silicon these days when we have access to so many cores.
Your understanding of computers is wrong..... You benchmark queen's have no idea what HT is good for.... Why does power have SMT8 etc.
 
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AMDK11

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I think Panther Lake is more of a Lunar Lake refresh. I don't think it has anything to do with ARL-R. After Arrow Lake, Intel's next major architecture is actually Nova Lake I presume.
I meant ArrowLake-R. This will be a LionCove with more L2/L3 memory or more e-cores. The basic improvements, if any, will be symbolic. Another new microarchitecture in NovaLake.
 
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Hitman928

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HT is useless these days. Especially when we have so many physical cores. HT comes into play *only* when all the cores are running full steam. Otherwise, it remains idle.

The scheduler (OS/Thread Director) activates HT to quickly preempt a already running thread when a physical core is no longer available. Even if a single core is available, HT remains idle. Now that we have so many cores, HT never comes into play.

In short, HT is useful mainly for running benchmarks and running massive multitasking loads like video encoding. Otherwise, it's pretty much waste of silicon these days when we have access to so many cores.

It is still useful for the low end of the consumer market. There is still a pretty decent chunk of volume that are 2 - 4 core CPUs and HT makes a big difference there and let's the maker offer them for cheaper than it would if they had to put additional cores there instead. Granted, it's the least profitable part of the market, but it still does noticeable volume. Maybe they'll get replaced with 1P-2P and 4E-6E type configs or something going forward but I'm not sure if that would really work out logistically.
 
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FlameTail

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Even SMT8000 is possible. In servers it's a different story altogether. Server CPU utilization is usually very high. In the order of 80% or above. The better the utilization, better the ROI. HT makes quite a difference in servers.

But not so in the case of clients. I can assure that almost 99.9% of the home/office computers in the world do NOT run at 80% of CPU utilization all the time. And in these systems, HT is a complete waste of silicon. Apple never cared about HT. ARM never cared about HT. They just went ahead and added more real cores instead. Intel is doing just that but a few years later. HT is useless when we have many real cores.

Which is why ARM server cores have SMT, while the client ones do not.
 

FlameTail

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It is still useful for the low end of the consumer market. There is still a pretty decent chunk of volume that are 2 - 4 core CPUs and HT makes a big difference there and let's the maker offer them for cheaper than it would if they had to put additional cores there instead. Granted, it's the least profitable part of the market, but it still does noticeable volume. Maybe they'll get replaced with 1P-2P and 4E-6E type configs or something going forward but I'm not sure if that would really work out logistically.

4P+4E like Apple has done is the way.
 

Hitman928

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Agree. But I very strongly feel Intel should stop manufacturing dual core & quad core parts. We're in 2024, and dual & quad core cpus are a disgrace. They just shouldn't exist anymore.

Education, embedded, and poor countries still want low cost solutions with just some basic functionality. Maybe all E-core solutions are good enough now to give a very good experience with Windows to fulfill these markets, but there is still a decent chunk of volume there, even if it isn't great margins and you still don't want to give a terrible experience if you can give a better solution for the same price (e.g. 2P (or even 1P)+4E would be better than 8E).

4P+4E like Apple has done is the way.

That's still significantly more silicon than just a 4P core with smt. The markets these chips get sold in primarily are very price sensitive. Apple doesn't really compete in those markets so they can make their low end chips more expensive.

Edit: Personally, I similarly hope that smt goes away now that we have so many cores available in general with area efficient cores as an option as well. I'd like to see AMD embrace smt-less designs and Intel embrace feature parity E-cores though I prefer more of Apple's approach where E-cores are treated like E-cores versus spam cores in the consumer market.
 
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Schmide

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Agree. But I very strongly feel Intel should stop manufacturing dual core & quad core parts. We're in 2024, and dual & quad core cpus are a disgrace. They just shouldn't exist anymore.
Go watch/read https://www.servethehome.com/ there are so many cases for quad core parts.

Especially when they include some of their edge accelerators. (QAT QuickAssist Technology compression/encryption )

https://www.intel.com/content/www/us/en/products/details/processors/atom/c.html
 
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DAPUNISHER

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Agree. But I very strongly feel Intel should stop manufacturing dual core & quad core parts. We're in 2024, and dual & quad core cpus are a disgrace. They just shouldn't exist anymore.
I have a $70 dual core Celeron Chromebook. We use it as a dedicated investments management and bill paying device. Works well enough for that.
 

dr1337

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Correct me if I am wrong but Intel hasn't actually made a dual core die in a good while, and no quad core dies since Alderlake. Even the single core 7305 is just the 2+8 die cut all the way down.

With how good the E cores are intel could make an absolutely tiny SOC that has 2 clusters/8 cores and would easily handle all the embedded and edge workloads going forward. But as it stands it seems like all the celeron and cheap chips they have now are just old/defective 14/10nm products repackaged.

And that makes sense to me because while a quad P core die would also still be small, the ASPs will still be low. In terms of new laptops such a chip will be forever stuck in low end territory. And why waste time+money on fabbing a new die for the low end market when your 'waste products' can fill that void instead.



And to address the idea that dual core chips are still fine, yeah, that's true. But also the used market is so massively saturated with them that it's weird to me someone would by a new chromebook instead of something like a used macbook or thinkpad. A market that bets on the consumer being uninformed sounds like a massive uphill battle. And thats why we see higher end laptops becoming the midrange norm, customers don't want dual cores and quad cores anymore, its 2024 not 2004.
 

jpiniero

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With how good the E cores are intel could make an absolutely tiny SOC that has 2 clusters/8 cores and would easily handle all the embeIdded and edge workloads going forward. But as it stands it seems like all the celeron and cheap chips they have now are just old/defective 14/10nm products repackaged.

Intel has that - Alder Lake-N. Although yes if you look at Amazon the best sellers (other than Apple) are mainly Intel stuff that's discontinued. Granted Corpos aren't buying from Amazon but it's probally a decent enough barometer of what Retail people buy.

Given how badly people break things, esp laptops... not sure used is such a good idea.
 
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Hulk

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I'm having fun trying to predict how Intel can get this done with Arrow Lake.
Here's the latest ARL "model."
Assume ~8% clock speed reduction for P turbo and all-core. Assume E cores maintain current top clock as Gracemont.

Assume 25% IPC increase for Lion Cove and 35% for Skymont.

The would yield an ARL part that is 12% better than RPL ST and 6% better MT.

25% for Lion Cove is not out of the realm of possibility but I think 35% for Skymont is out of bounds.
 

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H433x0n

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I'm having fun trying to predict how Intel can get this done with Arrow Lake.
Here's the latest ARL "model."
Assume ~8% clock speed reduction for P turbo and all-core. Assume E cores maintain current top clock as Gracemont.

Assume 25% IPC increase for Lion Cove and 35% for Skymont.

The would yield an ARL part that is 12% better than RPL ST and 6% better MT.

25% for Lion Cove is not out of the realm of possibility but I think 35% for Skymont is out of bounds.
There’s enough data out about ARL that we’ve got a good idea of what to expect.

It’s rumored that ARL-S will achieve 5.8ghz boost clocks. I’m not sure if I believe that but I do think it’s probably going to end up in the 5.6-5.8ghz range.

Lion Cove *effective* IPC is rumored to be between 14-18%. The core itself had a target of ~20% but due to tile overhead and additional latency you can subtract 2-6% from that figure. Skymont is supposed to get close to a 20% IPC increase, not sure about the frequency though.

Optimistic scenario (assuming they hit 5.8ghz) the real world 1T perf uplift is going to be 13-16% over RPL-S and 10-13% over RPL-R.

Pessimistic scenario (assuming they hit 5.6ghz) the real world 1T perf uplift is going to be 10-13% over RPL-S and 7-10% over RPL-R.

There’s supposedly 2 different power limits. The first has a PL2 in the 160-180W and the second PL2 is <220W. That second PL2 I’m not sure if it’s meant to be an “extreme” config or if it’s the 8P+32E SKU.
 

Hulk

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There’s enough data out about ARL that we’ve got a good idea of what to expect.

It’s rumored that ARL-S will achieve 5.8ghz boost clocks. I’m not sure if I believe that but I do think it’s probably going to end up in the 5.6-5.8ghz range.

Lion Cove *effective* IPC is rumored to be between 14-18%. The core itself had a target of ~20% but due to tile overhead and additional latency you can subtract 2-6% from that figure. Skymont is supposed to get close to a 20% IPC increase, not sure about the frequency though.

Optimistic scenario (assuming they hit 5.8ghz) the real world 1T perf uplift is going to be 13-16% over RPL-S and 10-13% over RPL-R.

Pessimistic scenario (assuming they hit 5.6ghz) the real world 1T perf uplift is going to be 10-13% over RPL-S and 7-10% over RPL-R.

There’s supposedly 2 different power limits. The first has a PL2 in the 160-180W and the second PL2 is <220W. That second PL2 I’m not sure if it’s meant to be an “extreme” config or if it’s the 8P+32E SKU.
Using the numbers you provided optimistically, Intel is going to have a tough sell with ARL. Even give it 5.8GHz ST and 5.5GHz MT and 20%/20% IPC uplift P's and E's with 2% tile penalty that will get them +14% ST but break even MT. This is of course using CB R23 as the model.

Now in reality that +14% ST increase is going to mean a lot when it comes to most applications. But they are still going to have to put a spin on rendering scores if this is close to the final specs.
 

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H433x0n

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Using the numbers you provided optimistically, Intel is going to have a tough sell with ARL. Even give it 5.8GHz ST and 5.5GHz MT and 20%/20% IPC uplift P's and E's with 2% tile penalty that will get them +14% ST but break even MT. This is of course using CB R23 as the model.

Now in reality that +14% ST increase is going to mean a lot when it comes to most applications. But they are still going to have to put a spin on rendering scores if this is close to the final specs.
It wouldn’t surprise me if the results end up pretty close to RPL-R while using half the power. I don’t think MT scores are that important past a certain point. It will become important to Reddit once Intel loses the pointless CB R23 supremacy. It's going to be so annoying seeing r/buildapc re-orient themselves and move the goal posts.

For what it's worth, a 14900K isn't actually running at 5.7ghz in CB R23 unless it's pulling well over 300W. I also only see a regression of 15% without HT in CB R23 (I go from 40K to 35K when I disable HT).
 

tamz_msc

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Interestingly, on the PES thread, there's a recent submission of desktop Phoenix. My lower binned quad core Tiger Lake laptop CPU is scoring 15-20 percent higher in efficiency in a lightweight load like GB5 compared to that score.