Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[OneEng2]

Are we seeing patterns already?

Only 2024 client cpu tiles (ARL/LNL) were outsourced because they didn't have a choice. And things are coming back to IFS next year. And if I'm right, as of now, almost all server cpu tiles too are not outsourced either. Even the upcoming DNR is on 18A-P I think. All IFS only. So what imaginary pattern are you talking about?


18A volume ramp should happen H2 next year. Starting then, I think IFS would be on a better/more solid foundation. Meaning, IFS would be in a lot better position than they have ever been in the last 10 years. Also, IFS has a High-NA lead over competition.

Certainly we have seen slippage in the Intel process roadmap even since the 5 nodes in 4 years thing came up. Then there was 14+++++ followed by 10++++ renamed to Intel 7, etc. While none of this means 18A is going to be abandoned for any tiles at all in 2025, it certainly presents one with ample reason to doubt that 18A will be a smooth and on-time launch. In fact, we have already seen the metrics for 18A relaxed significantly from original targets as well as 20A being dumped.

I am pulling for Intel. They really need 18A to go well.

 

[trivik12]

But they did, LNL is monolithic.

Is it though? I thought they used different tiles for CPU, GPU and SOC? where is the memory controller in Lunar Lake?

 

[adroc_thurston]

Is it though?

Yea.

I thought they used different tiles for CPU, GPU and SOC

That's MTL/ARL.

where is the memory controller in Lunar Lake?

On the CPU tile.
It's the one CPU+PCH combo, just on a 2.5D slab.

 

[Thibsie]

But they did, LNL is monolithic.

And without child. They do something well and it had to be a "oops, won't do it again !"
I dunno if Gelsinger is the messiah but if some magic has to happen, it'd better come quickly.

 

[jpiniero]

Does panther lake have laptop dGPU designs? or is it just arrow lake for two years there? Cause the latest rumor is that top panther lake die will be 4P+8E+4LPE like 12600H or smth

Presumably Bartlett?

 

[Thibsie]

Indeed! Now the only thing missing from your observations are a cross-tab of major features for each core (SMT, AVX512, etc).

I keep hearing how impressive the M4 and M3 are; however, neither one has SMT and neither one supports AVX512 (or 256 for that matter I believe).

Considering what they do well though, it seems to come down to an argument about how specific you want your CPU design to be to a particular market segment.

Seems like the M3/4 design is uniquely qualified for thin-and-light laptops and tablets, but totally useless for a DC processor design.

Zen5 on the other hand seems to cover bases up and down the market chain, but is not as good as M3/4 where the M3/4 is strongest. This makes a great deal of sense to me since AMD is targeting the high margin (and rapidly growing) DC market where M3/4 are not (As far as I know anyway).

Better where? Better how?

Mmm maybe.
OK, let's say QC Oryon and Apple M-cores are similar, at least compared to Zen cores. Correct ?
Since Oryon is really a server oriented core repurposed to serve client workloads, I wouldn't be that sure.

 

[GTracing]

But they did, LNL is monolithic.

Is it though? I thought they used different tiles for CPU, GPU and SOC? where is the memory controller in Lunar Lake?

Yea.

I think you have a different definition of monolithic than most people.

 

[poke01]

I think you have a different definition of monolithic than most people.

LNL isn’t monolithic it’s using tiles, better than MTL but still tiles. HX 370 and M4 are monolithic.

 

[GTracing]

LNL isn’t monolithic it’s using tiles, better than MTL but still tiles. HX 370 and M4 are monolithic.

Yeah, I agree. I'm confused why adroc is saying it's monolithic.

 

[fastandfurious6]

you need a good product not a high end product look at 4060/4070 lol it is not high end but Nvidia still makes nice money

apples and oranges

they want a piece of DLSS, CUDA and the #1 gpu company. otherwise AMD is better bang4buck

none of these apply for general purpose CPUs or Intel

 

[adroc_thurston]

I think you have a different definition of monolithic than most people.

Sticking PCH on the package does not make it a non-monolithic design. Hope that helps!

LNL isn’t monolithic it’s using tiles

Yeah it is, it's the old CPU + PCH setup, just on a 2.5D slab.

 

[Josh128]

Can any Arrow Lake or Lunar Lake owners run Dolphin Bench 5.0? Curious to see how it does there, havent seen it anywhere.

[Unofficial] New Dolphin 5.0 CPU benchmark - results automatically updated!

DISCLAIMER: The purpose of this thread is to use Dolphin and luabench as a general CPU benchmark that can used to determine a CPU architecture's relative capabilities in emulation-based workloads; it

forums.dolphin-emu.org

 

[Racan]

Can any Arrow Lake or Lunar Lake owners run Dolphin Bench 5.0? Curious to see how it does there, havent seen it anywhere.

[Unofficial] New Dolphin 5.0 CPU benchmark - results automatically updated!

DISCLAIMER: The purpose of this thread is to use Dolphin and luabench as a general CPU benchmark that can used to determine a CPU architecture's relative capabilities in emulation-based workloads; it

forums.dolphin-emu.org

I found this:

CPU Performance - Page 3 - LanOC Reviews

LanOC benchmarks and tests todays latest CPUs

lanoc.org

 

[poke01]

I found this:

CPU Performance - Page 3 - LanOC Reviews

LanOC benchmarks and tests todays latest CPUs

lanoc.org

Yep this is accurate. My 7700X does it in 182 seconds.

 

[coercitiv]

Sticking PCH on the package does not make it a non-monolithic design. Hope that helps!

Historically GPUs and MCs weren't part of the CPU die either, and we still considered them monolithic. Obviously what constitutes a "monolithic" chip is a moving target these days, and it would help to look at what the product is trying to achieve before assigning a label or the other. In the case of LNL the intent was to achieve a very similar effect to complete PCH integration on the die, the same way AMD did their mobile chips for a while now (which we also consider as monolithic, seems this term is very... inclusive). From this point of view one might consider LNL is not monolithic anymore, since the target has moved.

Going back to @trivik12 original observation though, I would agree with @adroc_thurston - LNL is optimally consolidated and integrating the PCH wouldn't help. To use the car analogies which we all love so so much, LNL has an engine problem and not a transmission problem. I'll see myself out.

 

[Racan]

Yep this is accurate. My 7700X does it in 182 seconds.

I don’t understand why their 9600X is faster than the 9700X though.

 

[lightmanek]

I don’t understand why their 9600X is faster than the 9700X though.

According to my wife, sometimes smaller is better ...

 

[darkswordsman17]

So Lunar Lake is the only chip that's gonna have the DRAM on package? What a baffling move, especially since it seems to have paid off for performance and efficiency.

They should have killed p cores with Arctic wolf itself taking care of everything. Reduce complexities and even go back to monolithic for laptop soc.

If performance is there I'd agree, but if not, then it could lead to Atom part 2 where companies will eschew it, especially now that there's very competitive options.

I do feel like Intel could benefit from simplifying their products some. Maybe they should do what I've been saying AMD should do. Go efficient in their consumer CPU cores, maybe they could go 12 or 16, with say half being able to clock extra low for low idle stuff. Then for gaming, build APUs, where you make cores targeting gaming performance, where they also share memory (maybe even large cache). That would give them a reason to keep dGPU, would let their dGPU standout. It should also be decent for other tasks, or take the same design and replace the GPU with AI, or if they can tweak their GPU to do that as well would make a larger market for them to sell to.

 

[poke01]

yeah no difference with and without AVX512:

9950X DDR5 6400 with AVX512 enabled in BIOS ((3512 / 23571): https://browser.geekbench.com/v6/cpu/8043533
View attachment 108413


9950X DDR5 6400 with AVX512 disabled in BIOS (3510 / 23613): https://browser.geekbench.com/v6/cpu/8044153
View attachment 108414

Can you test Geekbench 5.x.x please?

I believe AES-XTS takes advantage of AVX-512 which is missing in GB6.

 

[Rheingold]

But they did, LNL is monolithic.

Sticking PCH on the package does not make it a non-monolithic design. Hope that helps!

While the "monolithic" regarding the CPU might be debatable, the "on the package" regarding the PCH is misleading. While the memory is "on the package", the PCH is put on there in the same fashion as with ARL, with all the associated additional manufacturing steps and costs.

 

[reaperrr3]

I don’t understand why their 9600X is faster than the 9700X though.

Their 7600X is also faster than their 7700X and their 7900s are faster than their 7950X.

One possible explanation: The benchmark may be low-threaded but not really single-threaded, so having 2 cores per CCD disabled frees up just enough L3 for a tiny IPC boost, and/or thermal/power headroom to keep up turbo clocks more consistently.

 

[reaperrr3]

So Lunar Lake is the only chip that's gonna have the DRAM on package? What a baffling move, especially since it seems to have paid off for performance and efficiency.

Probably not in terms of margin, though. I remember in a previous call they hinted that LNL hurts(!) their margins, so it seems to be more expensive to make in this form than they can sell it at.

Then for gaming, build APUs,

That didn't even work for AMD, despite superior GPU IP.
Whether on Llano, Trinity, Kaveri, Carrizo or RR/Picasso, in hindsight AMD mostly threw margin away with those unneccessarily big iGPUs, because big APUs are inherently "neither fish nor flesh" products. Not fast enough for real gaming without tons of cache or wider mem interfaces, wasted silicon for most non-gaming workloads.

if they can tweak their GPU to do that as well would make a larger market for them to sell to.

They can't and won't, even if they had more skilled people and no layoffs/cost-cutting going on.
APUs as you envision them are simply extremely hard to monetize, as AMD has proven before (and my hunch is telling me that even Strix Halo won't exactly be a homerun in that regard).

The only point I agree with is that Intel should be smarter about how to invest their die area, especially for products they make at TSMC, where they can't even justify big dies with keeping their own fabs utilised.

 

[MoistOintment]

Yeah, PTL-

Does panther lake have laptop dGPU designs? or is it just arrow lake for two years there? Cause the latest rumor is that top panther lake die will be 4P+8E+4LPE like 12600H or smth

H (the 4+8+4) model will have dGPU options. 4+8+4 honestly makes more sense than 6+8 (the 2 LP-E cores are near useless in MTL/ARL) considering how close the E core to P core gap is getting and how area inefficient P cores are.

 

[csbin]

Z890 CUDIMM

https://twitter.com/x/status/1853371337173274624

 

[MarkPost]

Can you test Geekbench 5.x.x please?

I believe AES-XTS takes advantage of AVX-512 which is missing in GB6.

Sure

9950X PBO DDR5 6400 with AVX512 enabled in BIOS (2703 / 28719): https://browser.geekbench.com/v5/cpu/23027280


9950X PBO DDR5 6400 with AVX512 disabled in BIOS (2458 / 28569): https://browser.geekbench.com/v5/cpu/23027302


So, AVX512 are only implemented in AES-XTS ST, but not in MT