Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing Raptor Lake-U. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q1 2026.

		Intel Raptor Lake U	Intel Wildcat Lake 15W	Intel Lunar Lake		Intel Panther Lake 4+0+4
Launch Date		Q1-2024	Q2-2026	Q3-2024		Q1-2026
Model		Intel 150U	Intel Core 7 360	Core Ultra 7 268V		Core Ultra 7 365
Dies		2	2	2		3
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		Intel 18-A + Intel 3 + TSMC N6
CPU		2 P-core + 8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		4 P-core + 4 LP E-cores
Threads		12	6	8		8
Max Clock		5.4 GHz	4.8 GHz	5 GHz		4.8 GHz
L3 Cache		12 MB	6 MB	12 MB		12 MB
TDP		15 - 55 W	15 - 35 W	17 - 37 W		25 - 55 W
Memory		128-bit LPDDR5-5200	64-bit LPDDR5x-7467	128-bit LPDDR5x-8533		128-bit LPDDR5x-7467
Size		96 GB	48 GB	32 GB		128 GB
Bandwidth		83 GB/s	60 GB/s	136 GB/s		120 GB/s
GPU		Intel Graphics	Intel Graphics	Arc 140V		Intel Graphics
RT		No	No	YES		YES
EU / Xe		96 EU	2 Xe	8 Xe		4 Xe
Max Clock		1.3 GHz	2.6 GHz	2 GHz		2.5 GHz
NPU		GNA 3.0	17 TOPS	48 TOPS		49 TOPS

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[invisible_city]

Skymont looks awesome. But for Lion Cove, Intel's SMT yield was, what, ~25% or so? Maybe a bit less? Still, unless there's a big improvement somewhere else like area, seems a bit "one step forward, two steps back," does it not?

Intel hinted pretty heavily that they would not remove HT from Arrow Lake unless there was a net performance uplift to be gained on desktop workloads.

The 2 IP blocks discussed as being modular in Lion Cove were 1) hyperthreading, and 2) AVX 512. They stated that non-mobile designs would not need to sacrifice HT.

This is why they described Lion Cove as a uArch rather than a core.

 

[FlameTail]

Yeah 14% is Lunar Lake P-Core vs Meteor Lake P-Core not Lion Cove vs RWC

This generation x86 was kinda disappointing, eh?

Zen5 = 16% IPC, iso clock
LNL P-core = 14% IPC, clock regression (?)

 

[invisible_city]

FP theo

Skymont INT performance is great, but as far as FP goes I think it's roughly half throughput vs Raptor Cove (AVX256 needs to be split in 2 ops to execute on its FP units?).

They weren’t comparing to raptor cove with avx 512. FP throughout is theoretically doubled on Skymont (4*128), so may even be more performant on average fp workloads that aren’t specifically written with AVX in mind, but yeah it won’t be as good on tasks that benefit from AVX 512, vs server raptor cove (Emerald Rapids).

 

[cebri1]

 

[invisible_city]

Raptor Cove in mobile CPUs. What made you think I was switching to desktop parts on the fly and without mentioning it?

they mention it on the slide. It’s comparing Skymont attached to L3 to Raptor Cove. Skymont in lunar lake has no l3 cache.

 

[mikk]

By the way Intel says there is roughly 5% between the regular Skymont with access to LLC and Skymont LPE.

 

[Anhiel]

Looks like Intel went all out similar to Nvidia with adding every amount of various execution units possible along with all the front end expansion. In this light the +14% IPC seems a bit low but I guess the expansion impression is misleading because the ratio front end throughput isn't as much. It's great to see E-core IPC improvements are 10% more than expected.
This is gonna give Zen5 a run for the money. Then again Zen5 will likely beat it on cost.
Anyhow, it's good to see this major overhaul. Now, I'm excited to see what just tweaks alone could get out of these.

Edit: Just read Intel reserves +/- 10% margin of error for Skymont e-cores. Welp.

 

[poke01]

In this light the +14% IPC seems a bit low but I guess the expansion impression is misleading because the ratio front end throughput isn't as much.

it it low. Lion cove is mid. Skymont is where the uplifts are.

 

[FlameTail]

it it low. Lion cove is mid. Skymont is where the uplifts are.

Both "new generation" P-cores from Intel/AMD are mid, despite all the hype. However, Skymont being so strong was not something I anticipated.

 

[MarkPost]

https://imgur.com/EG3gPGB

So Intel states Lunar Lake will be released this july-september timeframe, and yet no real numbers nor real perfomance comparison? Just projections/estimates. WTF?

 

[SarahKerrigan]

https://imgur.com/EG3gPGB

So Intel states Lunar Lake will be released this july-september timeframe, and yet no real numbers nor real perfomance comparison? Just projections/estimates. WTF?

SPEC has to be marked as an estimate unless the number is part of an official result disclosure. Same reason Anandtech's SPEC numbers are referred to as estimates.

 

[Saylick]

By the way Intel says there is roughly 5% between the regular Skymont with access to LLC and Skymont LPE.

Source? Just want to document this for future reference.

 

[coercitiv]

So Intel states Lunar Lake will be released this july-september timeframe, and yet no real numbers nor real perfomance comparison? Just projections/estimates. WTF?

Intel's slides are the best I've seen in years in terms of useful information (from them). You can argue you don't believe them, and that would be fair game given their past behavior, but the format and quality of info presented has improved significantly.

And when it comes to their GPU keynotes, including for LNL, Tom Petersen is doing absolute wonders for Intel, especially in building trust with both media and the end consumer.

 

[Saylick]

That is from twit

JFC, WTFtech hires morons, I swear. Hassan couldn’t read the dang press slides accurately even when it’s right in front of him.

Skymont in LNL with 8MB Memory Side Cache vs Crestmont LP-E in MTL: +38% INT, +68% FP IPC


Skymont in LNL with 8MB Memory Side Cache vs Raptor Cove: +2% INT/FP IPC


Lion Cove in LNL vs Redwood Cove in MTL: +14% IPC, perf/W varies from +18% at lower power to +10% at higher power

 

[inf64]

The +-10% margin of error is hilarious though. In what universe is 10% acceptable margin of error?

 

[The Hardcard]

https://imgur.com/EG3gPGB

So Intel states Lunar Lake will be released this july-september timeframe, and yet no real numbers nor real perfomance comparison? Just projections/estimates. WTF?

They have to get in their final tweaks. All these companies are aggressively turning knobs. Now that AMD, Qualcomm, and Apple have outed their 2024 holiday season performance, Intel has a lot of adjustments to make.

 

[dullard]

https://imgur.com/EG3gPGB

So Intel states Lunar Lake will be released this july-september timeframe, and yet no real numbers nor real perfomance comparison? Just projections/estimates. WTF?

It comes down to the release date (to the public, not the release date to laptop manufacturers). SPEC rule 4.2 states that the CPU must be generally available within 3 months. If Lunar Lake is launched later in Q3, it would not likely be generally available to the public within that timeframe--especially since laptops take time to launch after the manufacturers receive the CPUs. Three months from the time the slide was made is August 13, 2024.

SPEC requires anything that does not meet the rules, such as rule 4.2, must be labeled as an estimate: "If the alleged value is not from a rule-compliant run, then it is an estimate." Heck, the estimate requirement specifically calls out the 3 month availability window in the definition.

Rule 4.2: https://www.spec.org/cpu2017/docs/runrules.html#rule_4.2 (scroll up a few lines from this link)
Estimate label is required if Rule 4.2 is not met: https://spec.org/fairuse.html#DefineEstimate (scroll up a few lines)

 

[Wolverine2349]

Meanwhile it's the reverse with Skymont and its lack of L3 (I think?).

Isn't L3 cache shared between all cores on a CPU die? Or is there something about SKymont that it has a lack of access to it. I mean there is probably a catch to e-cores performing as well as Golden COve or even Raptor Cove in IPC besides just well they only run at 4.6GHz. 4.6GHz is actually pretty decent and almost Golden Cove like. If overall raw performance across all workloads and latency and memory and such for gaming to be an all P core Golden Cove clock normalized equal (without HT as HT does not really matter for games for higher core count CPUs as long as cores are on same die with good core to core latency) if Lion Cove disabled. Its the L3 right making latency much worse if it is used without the P cores for non hybrid so not in real world a Golden Cove equal without the P cores and whole die enabled?

 

[AMDK11]

For LionCove, I expected the average IPC increase to be closer to 20% than 14%. Apparently the tiles and the disabled AVX512 cause the average to be lower than it could be. Zen 5 has AVX512, and yet the average increase is only 2 percentage points higher.

Another good sign is that resources were not increased excessively during the LionCove project, including: ROB from 512 to 576.

However, the strong reconstruction and expansion of the Front-end is impressive, including: the predictor is 8x larger than in GoldenCove!


I believe the starting point is a major overhaul of LionCove's core. We'll see what the next generations will show.

 

[sgs_x86]

Skymont in LNL with 8MB Memory Side Cache vs Raptor Cove: +2% INT/FP IPC

That is Skymont with LLC and on a RING. I am 99% sure that is Skymont from Arrow Lake. Where it sits on the ring bus and has access to the L3 cache.

 

[rgba]

Perf/Power curve for Lunar Lake, haven't seen it in the Anandtech article

 

[SarahKerrigan]

That is Skymont with LLC and on a RING. I am 99% sure that is Skymont from Arrow Lake. Where it sits on the ring bus and has access to the L3 cache.

Where are you getting that from? It's talking about an SLC, not the regular ring-connected distributed L3.

Edit: Yeah, looking closer at it, I see now. Mea culpa.

 

[invisible_city]

JFC, WTFtech hires morons, I swear. Hassan couldn’t read the dang press slides accurately even when it’s right in front of him.

Skymont in LNL with 8MB Memory Side Cache vs Crestmont LP-E in MTL: +38% INT, +68% FP IPC
View attachment 100465

Skymont in LNL with 8MB Memory Side Cache vs Raptor Cove: +2% INT/FP IPC
View attachment 100466

Lion Cove in LNL vs Redwood Cove in MTL: +14% IPC, perf/W varies from +18% at lower power to +10% at higher power
View attachment 100467

You can't read the slides either 🙂

The vs raptor cove is not Lunar Lake LP Skymont vs Raptor Cove, but an undisclosed (Arrow Lake) implementation where the Skymont cluster is on the ring bus (and shares L3 with P-cores)

 

[mxyztplk]

The +-10% margin of error is hilarious though. In what universe is 10% acceptable margin of error?

In a universe that contains beings known as attorneys?

 

[inf64]

In a universe that contains beings known as attorneys?

First post in 15 years, congrats man.

And no, it's hilarious margin of error, no matter if it's to cover their a**es legally.