Discussion Intel current and future Lakes & Rapids thread

[Geddagod]

https://twitter.com/x/status/1655593409464205312

Some info and guesses apparently

So the point of contention with this leak is the size of the L1 cache. Raichu claims it's 64KB L1D, which is a doubling of cache and would undoubtedly bring a latency impact. Locuza thinks it's 48KB, a 50% increase.
I started doing redwood cove die shot calculations a while back for fun, and if I paid attention I should have caught this earlier lol, but...
(GLC on the right, RWC on the left)
*Note L1I for RWC was preliminary, could be 48KB or 64KB.

64KB L1I could be true I think. While I'm not even close to the accuracy in estimations Locuza can prob bring, I do wonder if he made a mistake somewhere because I am using the same markings for the die shot he created, yet and coming up with way different estimations.

 

[nicalandia]

The Final Review is Up(Previous was a Preview) and is not looking great for Sapphire Rapids. Lets hope Granite Rapids can beat Threadripper Pro 5000 series

 

[Geddagod]

I'm getting major deja vu. Didn't pugetsystems already post a review of this? Not a previw, the actual review. They also included the lower core count models as well. Is this an update? Idk.
Regardless, interesting results. Uses 40% more power than AMD and scores 10% lower still in cb23. Yikes.
Overall, per core SPR looks to be as strong as TR but uses drastically more power, like 40-70% more with the top SPR sku. Don't know if MCM SPR is just extremely bad, mesh just scales terribly, or what it is, because GLC vs Zen 3 in the W2400 series looks to be equivalent in performance and efficiency.
Looking forward to what EMR can bring, because top end SPR just looks bad in comparison to... a what, 2 year old CPU?

 

[nicalandia]

I'm getting major deja vu. Didn't pugetsystems already post a review of this? Not a previw, the actual review. They also included the lower core count models as well. Is this an update? Idk.

On their Preview they used Beta Bios, now they are using Release Bios... Nothing Changed. Distribuiting A Huge Mesh over 4 Tiles is not efficient. That's why Granite Rapids is doing away with it

 

[Exist50]

That's why Granite Rapids is doing away with it

GNR looks to be doing basically the same thing, but with 3 even larger tiles instead of 4 smaller ones. I guess 5 if the mesh extends to the endcaps.

 

[nicalandia]

GNR looks to be doing basically the same thing, but with 3 even larger tiles instead of 4 smaller ones. I guess 5 if the mesh extends to the endcaps.

Sorry I meant Emerald Rapids...

 

[Geddagod]

So the point of contention with this leak is the size of the L1 cache. Raichu claims it's 64KB L1D, which is a doubling of cache and would undoubtedly bring a latency impact. Locuza thinks it's 48KB, a 50% increase.
I started doing redwood cove die shot calculations a while back for fun, and if I paid attention I should have caught this earlier lol, but...
(GLC on the right, RWC on the left)
*Note L1I for RWC was preliminary, could be 48KB or 64KB.
View attachment 80467
64KB L1I could be true I think. While I'm not even close to the accuracy in estimations Locuza can prob bring, I do wonder if he made a mistake somewhere because I am using the same markings for the die shot he created, yet and coming up with way different estimations.

Locuza confirmed he missed a couple blocks

https://twitter.com/x/status/1655982815526125589

So 64KB L1 I it is.
Kind of surprising tbh

 

[mikk]

Locuza confirmed he missed a couple blocks

https://twitter.com/x/status/1655982815526125589

So 64KB L1 I it is.
Kind of surprising tbh

It's funny when they argue with him in the first place and say no it's not 64KB you are wrong etc, I mean he is right basically everytime. And still there are people who think he is just a faker with no real sources like Bullsh1t_Buster.

 

[A///]

I've long suspected locuza was the same persons who leaked good data about intel processes and skus in the late 200s and again in the early 2011-2014 period before vnishing both times. both periods were also plaged by people sourcing fake slides and other misninformatoion.

 

[A///]

He kinda keeps worshiping AMD all the time. And tries to spreads too much FUD & hatred about nvidia & intel. What a low life. Looks like he's one of those AMD's paid leakers.

i was rereading my post which was a reply to you and then reread your post and then it hit me all of a sudden. didn't his anti intel sentiment reach manic levels a year ago when he got into that very public spat with someone from intel? It was a many months long very nasty very public row with an intel marketing executive Ryan Shrout? the anti intel behavior shot way up after that row.

 

[JoeRambo]

So 64KB L1 I it is.
Kind of surprising tbh

I feel like it is a change that makes a lot of sense for Intel. Currently they have 5 L1D cycle latency in GC cores. AMD has 4 cycle L1D latency and is also clocking >5.5Ghz. Is 48KB vs 32KB a proper compensation? I am not so sure.

It's really a replay of ADL having small and slow L2 in GC core that got fixed with Raptor Lake. If your cache is dead slow already, why not make it larger? @ 2MB per core it started to perform real well, due to hitting their horrible L3 ( that was also speed up ) less and suddenly whole chip was better.

64KB of L1D is big change, as long as they don't relax latency further and would feed their OoO monster better. Not hitting their weaker L2, means better perf and less power usage.

The real danger here i guess is decline in Intel's memory subsystem engineering overall, they might complicate latency in Skylake way, they might end up with 6 cycle latency across the board.
With "gems" like Saphire Rapids L3 subsystem that has 50ns latency you never know.

 

[SiliconFly]

i was rereading my post which was a reply to you and then reread your post and then it hit me all of a sudden. didn't his anti intel sentiment reach manic levels a year ago when he got into that very public spat with someone from intel? It was a many months long very nasty very public row with an intel marketing executive Ryan Shrout? the anti intel behavior shot way up after that row.

He's a text book drama queen! Will do anything to gather more likes for his channel!

But one thing really bother me. That idiot actually parroted some stuff i posted, slightly rephrased them for obvious reasons, and then claimed as though they were "facts" mentioned by a "source". What he fails to understand is that, most of the time these are just educated guesses based on publicly available information & not facts per se.

Now I know that our forum is one of his primary "sources". 🤓

 

[Hulk]

If they have in fact changed the L1 then that is a massive overhaul and I would expect other such large scale changes in the core.

 

[A///]

He's a text book drama queen! Will do anything to gather more likes for his channel!

But one thing really bother me. That idiot actually parroted some stuff i posted, slightly rephrased them for obvious reasons, and then claimed as though they were "facts" mentioned by a "source". What he fails to understand is that, most of the time these are just educated guesses based on publicly available information & not facts per se.

Now I know that our forum is one of his primary "sources". 🤓

wctech has lifted material posted here before and categorised it as an anonymous source before. I saw it not long ago. we should unleash nostra on mlid.

 

[DrMrLordX]

we should unleash nostra on mlid.

Not even MLID is that crazy.

 

[A///]

Not even MLID is that crazy.

but stupid enough.

 

[SiliconFly]

Just came across this recently...

Intel 4 HP libraries are highly optimized for higher performance. But they're still no match for Intel 7 UHP libraries (including the high drive current variant). Meaning, that squarely puts Intel 4 HP library's f-max at around 4.6 GHz to 4.8 GHz, +/- 200 MHz. I expect it to top out at 4.8 GHz max. That puts meteor lake chips in the i5 territory.

And all these days i was wondering why MTL topped-out at i5 (or core 5 ultra, etc). I don't think it's because of Intel 4 has capacity issues or yield issues or frequency regression. Looks like MTL & Intel 4 were designed that way.

And considering RWC architectural IPC increase is expected to be around single digit & L4 ADM is paired with the GPU, we can't expect much IPC increase either. IPC increase should be around 10% to 15% max at best (including L1, L2, L3 boost). This again puts MTL cpus right in the i5 territory. No wonder they capped it at i5.

I did some math and one thing kept popping up time and again. MTL's higher efficiency. That is, a 13th gen RPL i5-13500H is a 45W mobile part. And a 14th gen equivalent: 14500H mobile MTL cpu should deliver the performance of a 13500H at just 30W! Efficiency is off the charts!

Thats probably the reason why they want to call it Core 5 Ultra. Makes sense.

 

[Geddagod]

Just came across this recently...

Intel 4 HP libraries are highly optimized for higher performance. But they're still no match for Intel 7 UHP libraries (including the high drive current variant). Meaning, that squarely puts Intel 4 HP library's f-max at around 4.6 GHz to 4.8 GHz, +/- 200 MHz. I expect it to top out at 4.8 GHz max. That puts meteor lake chips in the i5 territory.

And all these days i was wondering why MTL topped-out at i5 (or core 5 ultra, etc). I don't think it's because of Intel 4 has capacity issues or yield issues or frequency regression. Looks like MTL & Intel 4 were designed that way.

And considering RWC architectural IPC increase is expected to be around single digit & L4 ADM is paired with the GPU, we can't expect much IPC increase either. IPC increase should be around 10% to 15% max at best (including L1, L2, L3 boost). This again puts MTL cpus right in the i5 territory. No wonder they capped it at i5.

I did some math and one thing kept popping up time and again. MTL's higher efficiency. That is, a 13th gen RPL i5-13500H is a 45W mobile part. And a 14th gen equivalent: 14500H mobile MTL cpu should deliver the performance of a 13500H at just 30W! Efficiency is off the charts!

Thats probably the reason why they want to call it Core 5 Ultra. Makes sense.

Idk why people keep on pushing the Intel 4 is HP so they can't hit high clocks. Intel 10nm UHP cells have like 5% higher Fmax than 10nm HP cells. The difference between UHP and HD is like >10%, but that's not what we are seeing here. Idk where people are getting the info that Intel 4 HP cells are significantly worse than Intel 7 UHP cells, like only hitting 80% Fmax. If someone can send me the link or something, I'll be glad.
Also if MTL has ADM. Your IPC estimates still seem pretty large, and also you only see an L1I increase in size, not L2 or L3, though there are some small improvements there. A 10-15% IPC boost, btw, is pretty much a standard ipc increase for Intel for a new arch, or slightly less by a percentage here of there.

 

[Geddagod]

Alleged Gigabyte Server roadmap

 

[H433x0n]

Just came across this recently...

Intel 4 HP libraries are highly optimized for higher performance. But they're still no match for Intel 7 UHP libraries (including the high drive current variant). Meaning, that squarely puts Intel 4 HP library's f-max at around 4.6 GHz to 4.8 GHz, +/- 200 MHz. I expect it to top out at 4.8 GHz max. That puts meteor lake chips in the i5 territory.

And all these days i was wondering why MTL topped-out at i5 (or core 5 ultra, etc). I don't think it's because of Intel 4 has capacity issues or yield issues or frequency regression. Looks like MTL & Intel 4 were designed that way.

And considering RWC architectural IPC increase is expected to be around single digit & L4 ADM is paired with the GPU, we can't expect much IPC increase either. IPC increase should be around 10% to 15% max at best (including L1, L2, L3 boost). This again puts MTL cpus right in the i5 territory. No wonder they capped it at i5.

I did some math and one thing kept popping up time and again. MTL's higher efficiency. That is, a 13th gen RPL i5-13500H is a 45W mobile part. And a 14th gen equivalent: 14500H mobile MTL cpu should deliver the performance of a 13500H at just 30W! Efficiency is off the charts!

Thats probably the reason why they want to call it Core 5 Ultra. Makes sense.

The ES2 silicon is already achieving 5.1ghz at 1.1V, if @OneRaichu is to be believed.

Edit: Wow his twitter posts creeps me out.

 

[coercitiv]

Alleged Gigabyte Server roadmap

That looks more like their exploding PSU roadmap.

 

[A///]

is all vnni disabled on 13th gen? what about gna?

The ES2 silicon is already achieving 5.1ghz at 1.1V, if @OneRaichu is to be believed.

Edit: Wow his twitter posts creeps me out.

there used to be a service online that bypassed the pop ups for twitter asking you to login so you could go through posts and likes without needing a twatter account. most of his posts seemed to be of cartoon freak proportioned animations in sexual poses. something isn't right with young people.

 

[jpiniero]

Not a fan of the Waifus?

 

[A///]

Not a fan of the Waifus?

what a strange question! they're bizzarre animals with massive elongated teeth, fat and slow but in a show of aggression will likely hurt you if they want to, never mind the silly bristle brush mustaches they all have. dreadful animals. seen plenty of beached walruses before, they die and stink to the heavens. their only use would be to render their fat for burning and their meat to be used in animal feed.

 

[Exist50]

is all vnni disabled on 13th gen?

I think they have AVX2 VNNI instructions supported by Gracemont.

what about gna?

GNA is its own separate accelerator. Though seems kind of pointless once they add MTL's VPU. Wonder if they'll end up dropping it.