Discussion Intel current and future Lakes & Rapids thread

[nicalandia]

Alderlake's high latency might be related to having too many cores on the ring bus. I doubt Raptorlake is better. That's 12 ring stops. Raptorlake needs to do way better just to keep it same as Alderlake.

As far as I am aware 12900K Alder Lake has 12 LCC/Ring Stops, one Stop for each P core and a total of 4 for the pair quad e cluster for a total of 12, Rocket Lake will be adding four more stops.

 

[igor_kavinski]

PSA: Rocket Lake is in the past. Raptor Lake is the soon-to-be-released one.

 

[jpiniero]

Even ignoring the question of how the atom modules would scaling in such a config, that wouldn't work for mobile. They're hemmed in on the y dimension.

Make the package size bigger?

As far as I am aware 12900K Alder Lake has 12 LCC/Ring Stops, one Stop for each P core and a total of 4 for the pair quad e cluster for a total of 12, Rocket Lake will be adding four more stops.

It's one hop per quad core, so Raptor is 12. Plus the IGP has a stop too.

 

[pakotlar]

PSA: Rocket Lake is in the past. Raptor Lake is the soon-to-be-released one.

People have trouble with reading and thinking, PSAs are needed sometimes.


On topic, https://wccftech.com/intel-14th-gen...e-for-tgpu-used-in-14th-gen-arrow-lake-rumor/

why would they do this, if there weren’t issues with N3?

 

[pakotlar]

So Intel's issues are not due to poor leadership decisions? Who's to blame for this?

If the company is failing leadership is at fault, full stop, I agree with you.

 

[pakotlar]

Actually what I think most folks are missing out on is how far behind TSMC is on their original N3 roadmap.

TSMC was supposed to be in full ramp N3 production late 2021. We should have 3nm iPhones coming out in two months, but we don't. And when they do come out in 2023, only the most expensive iPhones will be 3nm. So maybe half of what was originally thought.

Anyway, I think they are in a very slow, slower than originally planned for 2021, late 2022 production run for Apple and Intel, and won't ramp like their original projections until late 2023.

Now this gives Intel and Samsung a reprieve. I don't care for Samsung and its node name hijinx though, their "3nm" node is about like TSMCs enhanced N5 aka N4.

Intel's 4 node is reportedly superior to TSMC N4, so if Intel ships functioning 'Intel 4' node chips in 1H2023 - reality will be that they will have the best x86 node with a shipping product in the consumer space at that time. Might not last long, but it'll be the first time they could say that in over 5 years.

Regression to the mean affects everyone. Intel’s mean execution is pretty similar or better to TSMCs. TSMC has been outperforming for 5 years, wouldnt be the biggest shock if they hit a foul ball or 2.

 

[DrMrLordX]

I still think Raptor Lake, being the last monolithic die CPU for consumers, is likely to become a long-living legend and will be top dog in certain workloads for a very very long time.

It's going to be the last upgrade for consumer-level Intel users regardless of whether it's "top dog" or "living legend". Meteor Lake is unlikely to offer much to the desktop. People will have to wait for Arrow Lake in 2024.

 

[Doug S]

Actually what I think most folks are missing out on is how far behind TSMC is on their original N3 roadmap.

TSMC was supposed to be in full ramp N3 production late 2021. We should have 3nm iPhones coming out in two months, but we don't. And when they do come out in 2023, only the most expensive iPhones will be 3nm. So maybe half of what was originally thought.

When did TSMC ever say that N3 would ramp in late 2021? Show us a link where TSMC officially stated that (i.e. rather than some Digitimes rumor) You can't, because they never did. The first commitment they made for mass production was "H2 2022", and that is when N3 will enter mass production, with the first finished wafers early next year. Or you are confusing with their commitment for the N3 risk production ramp, which did indeed happen late last year.

Entering mass production in "H2 2022" represents about a six month delay from the timeline they've had for their last few process generations, which have delivered the first finished wafers in late Q2 / early Q3, to match Apple's iPhone product cycle. It was a only a slip from everyone's expectations, and may well have represented a slip from their internal roadmap - but what counts are your public commitments, and there was no slip there.

Anyway, Intel would be positively f-ing ecstatic if they could deliver on their Intel 3 / 20A / 18A roadmap with only a six month slip! And a lot of us would be surprised if they only slipped that far.

 

[shady28]

Google it yourself.

 

[Exist50]

@Exist50 Rocketlake is not a bad analogy in that it'll be perceived that bad in the market before a big jump occurs which claws back most of the deficit.

Eh, I don't know. Rocket Lake got particularly poor feedback because it was a regression from Comet Lake in some ways. Raptor Lake won't get quite that degree of mockery.

As far as I am aware 12900K Alder Lake has 12 LCC/Ring Stops, one Stop for each P core and a total of 4 for the pair quad e cluster for a total of 12, Rocket Lake will be adding four more stops.

Nope, it's one stop per each P-core or 4 E-core cluster. So 10 for Alder Lake, and 12 for Raptor Lake. And as jpiniero remind me, +1 for the GPU on those products as well, though it looks like MTL is moving it off the ring.

Make the package size bigger?

Bigger package => bigger motherboard => smaller battery. That's really not a tradeoff you want to force in mobile.

 

[Exist50]

On topic, https://wccftech.com/intel-14th-gen...e-for-tgpu-used-in-14th-gen-arrow-lake-rumor/

why would they do this, if there weren’t issues with N3?

Let me reference myself a few weeks ago.

N3 was never the plan for MTL, but I look forward to the rumor mongers attempting to claim otherwise when it launches. To cover their failed predictions, if nothing else.

It seems like some are trying to get in early. How cute.

 

[Exist50]

Google it yourself.

View attachment 65494

None of those "articles" reference TSMC's actual statements. At most, they reference the reasonable expectation (and probably internal roadmap) that N3 would reach mass production ~Q2, but TSMC never officially claimed that. They've done a very good job of providing accurate info to the public.

 

[IntelUser2000]

Eh, I don't know. Rocket Lake got particularly poor feedback because it was a regression from Comet Lake in some ways. Raptor Lake won't get quite that degree of mockery.

I was quoting you talking about Emerald Rapids not client.

 

[Exist50]

I was quoting you talking about Emerald Rapids not client.

Oh, yeah. Well, same thing. Emerald Rapids isn't going to get actively derided like Rocket Lake; people just won't care about it when Genoa exists.

 

[shady28]

None of those "articles" reference TSMC's actual statements. At most, they reference the reasonable expectation (and probably internal roadmap) that N3 would reach mass production ~Q2, but TSMC never officially claimed that. They've done a very good job of providing accurate info to the public.

As a matter of fact, the very first article does exactly that.

 

[IntelUser2000]

Oh, yeah. Well, same thing. Emerald Rapids isn't going to get actively derided like Rocket Lake; people just won't care about it when Genoa exists.

I am not sure if it makes a big difference. Sapphire Rapids is already seen as a big misstep by many. Emerald Rapids is a minimal gain on top of that. With the bugs EMR is basically the original SPR, launching many months after Genoa and same time as Genoa-X.

EMR better be a 72 core version like the rumors for original SPR. Ideally they would skip it to hasten GNR in select segments.

Competition-wise, it's like if we went from Rocketlake to a 8 core Tigerlake. Ehh, it's better but it's still in a massively losing position. The expectation that improved uarch would make up for core count differences compared to CML didn't happen either. I thought it should have been low single digit percentages, but the actual gap was much greater. Nevermind the power use.

 

[itsmydamnation]

As a matter of fact, the very first article does exactly that.

View attachment 65498

i would work to understand the bias of the person you are quoting. If you actually look and try and trace back to TMSC statements you can see the dishonest extrapolation Arne has made. And if you know who Arne is that isn't at all surprising.

You can even see it clear as day in the words you have quoted. "As compared with 5-nanometer".

 

[Doug S]

As a matter of fact, the very first article does exactly that.

View attachment 65498

So they said "it was a delay as compared with 5 nanometer" but not they did not say it was a delay from their previous statements. Because they had never made any official statements that N3 would be in mass production in H1 2022. It was only a "delay" from the point of view of outside beliefs/expectations.

Even then they say "3 to 4 months" which hardly matches your "how far behind" language where you compare it to Intel - which had a delay of 3 to 4 YEARS from their original roadmap for 10nm!

I say again, post a link where TSMC is stating N3 will enter mass production in late 2021 which is what you claimed. Or even where they state it will enter mass production in H1 2022. You will not, because the first official communication about its timeline said it would be H2 2022.

When they said that, people were talking about a delay but it was only a delay based on outside expectation. That quote you reference was confirming the "delay" of 3 to 4 months from the outside expectation, which would be late Q2 or early Q3 to sync up with Apple's iPhone schedule.

 

[LightningZ71]

There is also a stop on the Intel ring bus design for the IMC. Granted, it's a required standard, but it still counts. If memory serves, the single biggest ring that I have seen from Intel was on one of their past Xeon V4 products which I believe was 12 cores, one memory controller, a PCI root, two ring interconnect stations and one space for the external QPI link station. The single ring has been proven to allow 17 stations and a hugher speed, dual ring should be good to at least 17 and likely 20. On a typical client cpu, that's one pci root, one memory controller, one iGPU and up to 14-17 cores/quads. This means that 8 cores and 4 quads is no sweat, and going to 4 more quads isn't outlandish. 8 P cores and 32 e cores would be a MT monster.

 

[Heartbreaker]

People have trouble with reading and thinking, PSAs are needed sometimes.


On topic, https://wccftech.com/intel-14th-gen...e-for-tgpu-used-in-14th-gen-arrow-lake-rumor/

why would they do this, if there weren’t issues with N3?

WCCFTech is basically just a dumping ground for any Rumor. Intel was pretty explicit that there is no delay on Meteor Lake:

Intel denies Meteor Lake is delayed to 2024, says consumer chips will launch in 2023

However, Intel is flatly denying those rumors today, with spokesperson Thomas Hannaford clarifying to The Verge that not only are they untrue, but that Meteor Lake will actually ship, launch, and be available to consumers in 2023.

Further, TSMC commented that there have been no order changes on 3nm:

https://www.tomshardware.com/news/tsmc-comments-on-intel-n3-orders-report

 

[witeken]

Let's directly refer to what TSMC said:

Okay. My first question is regarding 3-nanometer ramp-up for second half, starting from second half next year. I recall the 7-nanometer ramp-up in year 2018 second quarter with some revenue contribution and the 5-nanometer in second quarter last year, year 2020. But it seems like 3-nanometers clearly some delay for second half next year. So I want to ask, is that because the technology difficulty, we cannot ramp up in second quarter or we don't have a big customer to use 3-nanometer at the beginning stage that's why we push back the ramp-up in second half next year?

Andrew, you have a very good observation and you calculate that, yes, about 3 to 4 months is a delay as compared with 5-nanometer.

Since N5 entered HVM in April 2020, the statement directly, unambiguously implies that TSMC intended to put N3 in HVM in July-August 2022. However, since TSMC is only expecting N3 revenue in Q1'23, this has been further postponed to (late) Q4 2022. This has been further confirmed by reports that N3 only started risk production in (late?) November 2021.

Conclusion: TSMC claimed N3 HVM would start in July-August, and clearly this isn't happening. N3 is both delayed compared to N5 as well as compared to TSMC's prior expectations.

None of those "articles" reference TSMC's actual statements. At most, they reference the reasonable expectation (and probably internal roadmap) that N3 would reach mass production ~Q2, but TSMC never officially claimed that. They've done a very good job of providing accurate info to the public.

i would work to understand the bias of the person you are quoting. If you actually look and try and trace back to TMSC statements you can see the dishonest extrapolation Arne has made. And if you know who Arne is that isn't at all surprising.

You can even see it clear as day in the words you have quoted. "As compared with 5-nanometer".

So they said "it was a delay as compared with 5 nanometer" but not they did not say it was a delay from their previous statements. Because they had never made any official statements that N3 would be in mass production in H1 2022. It was only a "delay" from the point of view of outside beliefs/expectations.

Even then they say "3 to 4 months" which hardly matches your "how far behind" language where you compare it to Intel - which had a delay of 3 to 4 YEARS from their original roadmap for 10nm!

I say again, post a link where TSMC is stating N3 will enter mass production in late 2021 which is what you claimed. Or even where they state it will enter mass production in H1 2022. You will not, because the first official communication about its timeline said it would be H2 2022.

When they said that, people were talking about a delay but it was only a delay based on outside expectation. That quote you reference was confirming the "delay" of 3 to 4 months from the outside expectation, which would be late Q2 or early Q3 to sync up with Apple's iPhone schedule.

 

[Exist50]

Let's directly refer to what TSMC said:


Since N5 entered HVM in April 2020, the statement directly, unambiguously implies that TSMC intended to put N3 in HVM in July-August 2022. However, since TSMC is only expecting N3 revenue in Q1'23, this has been further postponed to (late) Q4 2022. This has been further confirmed by reports that N3 only started risk production in (late?) November 2021.

Conclusion: TSMC claimed N3 HVM would start in July-August, and clearly this isn't happening. N3 is both delayed compared to N5 as well as compared to TSMC's prior expectations.

I'm clearly wasting my time responding, but as covered here several times over, TSMC never once publicly promised that N3 would be on the same schedule as N5, and the current timeline is perfect in keeping with what they have said.

 

[MadRat]

Cache is the simplest product to validate on a new process. Just seems natural to scale cache products up to justify getting a process out the door at the earliest stage. Starts your path to the black a bit sooner than conventional development models.

 

[nicalandia]

Nope, it's one stop per each P-core or 4 E-core cluster. So 10 for Alder Lake, and 12 for Raptor Lake. And as jpiniero remind me, +1 for the GPU on those products as well, though it looks like MTL is moving it off the ring.

Anantech speculated that it had 12 LLC/Ring Stops because when Intel Disabled one of the quad cluster in the 12700k the CPU lost 5 MiB of L2 Capacity instead of losing just 3

 

[LightningZ71]

It's more likely that the ring has (8 P core stops, 4 quad cluster stops, 1 iGPU stop, 1 memory controller stop and one PCIe controller complex stop) 15 stops. That makes it just shy of the Xeon V4 XCC primary cpu ring in size. Granted, this ring runs much faster and is two loops, so it should be more efficient.