Discussion Intel current and future Lakes & Rapids thread

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shady28

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AMD has not exactly been an early adopter of TSMC's processes, so I doubt many were expecting N3 CPUs from them in 2023 regardless of whether they started N3 mass production in Q3 or Q4 of this year.
AMD has traditionally been exactly 1 year behind Apple's adoption of the newest node. This is not new.

Apple itself has been doing tick-tock on nodes/arch since the A4. The longest they stay on any one node for new iPhone generations has been two years. They have done moves to enhanced versions of nodes in less than one year before as well, like 20nm->16nm which is the same node + FinFet in TSMC/Samsung speak. It is really an enhanced 20nm.

This would be just like the rumored 'N5->N4' move. N4 is just an enhanced N5. But that is one year to the next. They have always gone to a major new node every 2 years.

Until this year. This will be the 3rd year Apple is using the same node, for the first time, ever.

But yeah, everything is fine, TSMC can do no wrong, Intel will never catch them, and so on and so forth.

I am just here to see how the cognitive dissonance plays out.

And for reference :

1660223872157.png
 
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dullard

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May 21, 2001
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Yes, Intel is working with TSMC 3 nm. That much is true. But that is not addressing the key point: any shred of evidence that Meteor Lake was ever using N3. Meteor Lake is not mentioned in either of those two links. This is a quote from one of them: "Intel has already confirmed that it is cooperating with TMSC for the product lineup for 2023, but left it open as to which chips and which manufacturing technologies are the focus" I believe those two links came from this source which provides no evidence although it does mention Meteor Lake at least: https://ctee.com.tw/news/tech/552277.html

I'll ask again, is there any evidence that these are for Meteor Lake? Until there is solid evidence of that, I'll have to rely on the leaked Intel slide showing that those two links you provided are regarding Arrow Lake. https://forums.anandtech.com/threads/intel-current-and-future-lakes-rapids-thread.2509080/post-40815262
 
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Joe NYC

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Yes, Intel is working with TSMC 3 nm. That much is true. But that is not addressing the key point: any shred of evidence that Meteor Lake was ever using N3. Meteor Lake is not mentioned in either of those two links. This is a quote from one of them: "Intel has already confirmed that it is cooperating with TMSC for the product lineup for 2023, but left it open as to which chips and which manufacturing technologies are the focus" I believe those two links came from this source which provides no evidence although it does mention Meteor Lake at least: https://ctee.com.tw/news/tech/552277.html

I'll ask again, is there any evidence that these are for Meteor Lake? Until there is solid evidence of that, I'll have to rely on the leaked Intel slide showing that those two links you provided are regarding Arrow Lake. https://forums.anandtech.com/threads/intel-current-and-future-lakes-rapids-thread.2509080/post-40815262
With all the denials that the N3 was for Meteor Lake (and that it is delayed / cancelled), there is one crucial info missing:

If the H2 2022 production capacity was not for Meteor Lake, what it for? When will we see this product for sale?
(would have to be H1 2023)
 

Doug S

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H2 2023 launch of N3E would be too late for Apple 2023 model iPhone. There was some other article that mentioned that Apple will wait until the 2024 iPhone model to adopt this node.

So, without Apple using it for its major product, there should be capacity for HPC customers.

There were rumors last spring (which TSMC appears to have later confirmed) that progress on N3E is ahead of schedule and it will be pulled in to Q2.
 

Joe NYC

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There were rumors last spring (which TSMC appears to have later confirmed) that progress on N3E is ahead of schedule and it will be pulled in to Q2.
In that case, it should be possible to launch the 2013 iPhone model on N3E. We will what Apple decides.
 

jpiniero

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Oct 1, 2010
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Apple is probably using N4P for the 2023 iPhone, which performance and power is claimed to be pretty close to N3 while being cheaper.
 

Exist50

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Apple is probably using N4P for the 2023 iPhone, which performance and power is claimed to be pretty close to N3 while being cheaper.
At Apple's volumes, the area savings of N3 translate into a pretty substantial reduction in wafer count. Plus some low power benefits from the base N3B, and everything N3E adds on top. Besides, even if it's more expensive on paper, TSMC needs someone to use the node, and I'm sure they'll negotiate a price to match.
 
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repoman27

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AMD has traditionally been exactly 1 year behind Apple's adoption of the newest node. This is not new.

Apple itself has been doing tick-tock on nodes/arch since the A4. The longest they stay on any one node for new iPhone generations has been two years. They have done moves to enhanced versions of nodes in less than one year before as well, like 20nm->16nm which is the same node + FinFet in TSMC/Samsung speak. It is really an enhanced 20nm.

This would be just like the rumored 'N5->N4' move. N4 is just an enhanced N5. But that is one year to the next. They have always gone to a major new node every 2 years.

Until this year. This will be the 3rd year Apple is using the same node, for the first time, ever.

But yeah, everything is fine, TSMC can do no wrong, Intel will never catch them, and so on and so forth.

I am just here to see how the cognitive dissonance plays out.

And for reference :



View attachment 65695
You're missing the forest for the trees. Every new A series introduces an updated microarchitecture and targets the best available process. If TSMC takes three years instead of two between process families / full nodes, Apple will be on that node for three years as well. The gap between 16FF and N7 was three years. Apple taped out the A9 on both Samsung 14LPE and TSMC 16FF, the A10 Fusion on TSMC 16FFC, and the A11 Bionic on TSMC 10FF. That's three years on one process family.

The A14 was on N5, the A15 was on N5P, and the A16 will be on N4. Same deal.

You're talking about "cognitive dissonance" while trying to convince others that Intel is somehow executing according to their public roadmap and TSMC is not? I do not think that phrase means what you think it means.
 

shady28

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You're missing the forest for the trees. Every new A series introduces an updated microarchitecture and targets the best available process. If TSMC takes three years instead of two between process families / full nodes, Apple will be on that node for three years as well. The gap between 16FF and N7 was three years. Apple taped out the A9 on both Samsung 14LPE and TSMC 16FF, the A10 Fusion on TSMC 16FFC, and the A11 Bionic on TSMC 10FF. That's three years on one process family.

The A14 was on N5, the A15 was on N5P, and the A16 will be on N4. Same deal.

You're talking about "cognitive dissonance" while trying to convince others that Intel is somehow executing according to their public roadmap and TSMC is not? I do not think that phrase means what you think it means.
Try again. I said Apple switches to an entirely new node every 2 years, with partial node upgrades sometimes, until now.

Apple A7 = 20nm <- Major node
Apple A8 = 20nm

Apple A9 = 16nm Samsung / 14nm TSMC <- Major node
Apple A10 = 16nm TSMC FFT <- minor node

Apple A11 = TSMC 10nm <- Major node

Apple A12 = TSMC N7 <- Major node
Apple A13 = TSMC N7

Apple A14 = TSMC N5 <- Major node
Apple A15 = TSMC N5
Apple A16 = N5 or N4 <- N4 is a minor node

The N3 A17 is only expected to be in the top two iPhone models in 2023.

Do you see the pattern change. It's very obvious.

Why did you miss it.
 

repoman27

Senior member
Dec 17, 2018
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There were rumors last spring (which TSMC appears to have later confirmed) that progress on N3E is ahead of schedule and it will be pulled in to Q2.
TSMC has consistently said that N3E volume production is scheduled for 1 year after N3. When asked during the 1Q22 earnings call about potentially pulling N3 in, C.C. Wei said:
I mean that our N3E result is quite good. And the progress is actually -- is ahead of our schedule. And pull-in, yes, we are considering that. So far, I still did not have a very solid data to share with you that how many months we can pull in. But yes, it's in our plan.
However, during the 2Q22 call, the exact wording around N3E was:
[V]olume production is scheduled for around 1 year after N3.
Seeing as volume production for N3 is clearly 4Q22 at this point, there is little to no chance of N3E arriving in time for the 2023 iPhone. Also, Apple doesn't care about most of what N3E brings to the table; they're fine with N3 being higher cost / higher density / narrow process window.
 
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repoman27

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Try again. I said Apple switches to an entirely new node every 2 years, with partial node upgrades sometimes, until now.

Apple A7 = 20nm <- Major node
Apple A8 = 20nm

Apple A9 = 16nm Samsung / 14nm TSMC <- Major node
Apple A10 = 16nm TSMC FFT <- minor node

Apple A11 = TSMC 10nm <- Major node

Apple A12 = TSMC N7 <- Major node
Apple A13 = TSMC N7

Apple A14 = TSMC N5 <- Major node
Apple A15 = TSMC N5
Apple A16 = N5 or N4 <- N4 is a minor node

The N3 A17 is only expected to be in the top two iPhone models in 2023.

Do you see the pattern change. It's very obvious.

Why did you miss it.
TBH, I was thinking of 12nm which is part of the 16nm family. However, I would still hesitate to characterize 10nm as a "Major" node, seeing as it was not broadly adopted and only around for a hot minute. Did anyone other than Apple even use it?

The top two iPhone models are also expected to outsell platforms with tiny little Intel 4 CPU tiles in 2023 as well.

The pattern I indicated (new microarchitecture, best available process) holds true for every A series SoC, and Apple always leverages any available intranode improvements. What difference does it make if TSMC takes 3 years between process families? That was part of their roadmap. Shrinks are getting harder. The first product on Intel 10nm reached PRQ in Q4'17. The first product on Intel 4 will reach PRQ at least 5 years after that. That's 5+ years for one "Major node".
 

shady28

Platinum Member
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TSMC 10nm was 82% more dense than their 16nm.

That's a major node.

And for 2022, it's actually worse than I described. Most of the iPhones will still be on the A15.

Glad I got an iPhone 13, this disruption extends its lifespan a bit.



1660244014909.png


1660244337324.png


1660246549382.png
 
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Markfw

CPU Moderator, VC&G Moderator, Elite Member
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There is one for general foundries discussion which would fit perfectly.
This is a mod request. Since you all have correctly asked that this discussion use that thread, please refer all replies here on that subject to that thread. I appreciate you having this discussion rerouted, and I can't automatically move replies for this reason myself or issue warnings, so this is a voluntary request to keep up the good work and use that thread for the discussion of TSMC and Intel/N3.

This thread is for the CPUs'.
 

nicalandia

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This is a mod request. Since you all have correctly asked that this discussion use that thread, please refer all replies here on that subject to that thread. I appreciate you having this discussion rerouted, and I can't automatically move replies for this reason myself or issue warnings, so this is a voluntary request to keep up the good work and use that thread for the discussion of TSMC and Intel/N3.

This thread is for the CPUs'.
I can't believe how those posters just buried my post about the resent submission of a Release Sample of Sapphire Rapids 8470C and ES sample of The Xeon W9-3495X

Intel Xeon W9-3495X : 1477



Xeon Platinum 8473C: 1375



Threadripper PRO 3995WX: 1325
 

Markfw

CPU Moderator, VC&G Moderator, Elite Member
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I can't believe how those posters just buried my post about the resent submission of a Release Sample of Sapphire Rapids 8470C and ES sample of The Xeon W9-3495X

Intel Xeon W9-3495X : 1477



Xeon Platinum 8473C: 1375



Threadripper PRO 3995WX: 1325
And what is the 7702/7742 EPYC or the 5995wx scores ? Or Milan ? Or Genoa ?

Yes, I know this is an Intel thread, but if you are going to score the new Xeons, you should compare it to their competition.
 
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nicalandia

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Yes, I know this is an Intel thread, but if you are going to score the new Xeons, you should compare it to their competition.
I will post them as soon as they show up(on their respective thread)


I will say this. Raptor Cove Core is shaping out to be the Best Core Intel have and will release for Enthusiast/High end in the next 2 years. Because The castrated core on Sapphire Rapids is shaping out to be just a big disappointment due to Intel design choices and If design choices are not changed Emerald Rapids will fair no better
 

Exist50

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I will post them as soon as they show up(on their respective thread)


I will say this. Raptor Cove Core is shaping out to be the Best Core Intel have and will release for Enthusiast/High end in the next 2 years. Because The castrated core on Sapphire Rapids is shaping out to be just a big disappointment due to Intel design choices and If design choices are not changed Emerald Rapids will fair no better
I think you're reading too much into noisy results. Pretty much the only thing Raptor Cove adds over Golden Cove is the upgrade to 2MB of L2, which SPR already has. At this point we have most of the information needed to make some good guesses about where it'll fall.
 

nicalandia

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I think you're reading too much into noisy results. Pretty much the only thing Raptor Cove adds over Golden Cove is the upgrade to 2MB of L2, which SPR already has. At this point we have most of the information needed to make some good guesses about where it'll fall.
You seem to know or have some understanding on CPU Design. On a CPU Core is the L2 Cache always bigger than L1 and Smaller than L3? What would happen if the L2 was Smaller than L1 or Bigger than L3?
 

Exist50

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You seem to know or have some understanding on CPU Design. On a CPU Core is the L2 Cache always bigger than L1 and Smaller than L3? What would happen if the L2 was Smaller than L1 or Bigger than L3?
Certainly I can't think of any design where the L2 is smaller than the L1. There's no technical reason why you couldn't build one (assuming non-inclusive), but it would provide only a minor extra hit rate vs the L1, and almost certainly add latency to L3 or memory. Might very well be worse than not having one at all, and would definitely be a sub-optimal use of resources.

Same logic generally applies to L2 and L3... but if L3 is shared by different IPs (really, more of a system cache), you can do some interesting things by using it for data passing without going all the way out to memory. That's the only use case I can think of for a combined L3 smaller than an individual IP's L2, though it's plenty possible I'm missing one.
 
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nicalandia

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Certainly I can't think of any design where the L2 is smaller than the L1. There's no technical reason why you couldn't build one (assuming non-inclusive), but it would provide only a minor extra hit rate vs the L1, and almost certainly add latency to L3 or memory. Might very well be worse than not having one at all, and would definitely be a sub-optimal use of resources.

Same logic generally applies to L2 and L3... but if L3 is shared by different IPs (really, more of a system cache), you can do some interesting things by using it for data passing without going all the way out to memory. That's the only use case I can think of for a combined L3 smaller than an individual IP's L2, though it's plenty possible I'm missing one.
Say you have two similar Core processors at the uArch Level Processor A and B. Processor. Processor A has 1MiB of L2 and 0.94 MiB of L3. Processor B has 1MiB of L2 and 1.5MiB of L3. Which on is expected to perform better when fully loaded?
 

Exist50

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Say you have two similar Core processors at the uArch Level Processor A and B. Processor. Processor A has 1MiB of L2 and 0.94 MiB of L3. Processor B has 1MiB of L2 and 1.5MiB of L3. Which on is expected to perform better when fully loaded?
The latter, of course. Just saying, you are aware neither of those are the numbers for SPR/RPL, even on a core per basis, right? And then you need to consider that L3 is shared, and SPR has a lot more cores...
 

nicalandia

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The latter, of course. Just saying, you are aware neither of those are the numbers for SPR/RPL, even on a core per basis, right? And then you need to consider that L3 is shared, and SPR has a lot more cores...
The Alder Cove Cores on Sapphire Rapids are so constrained and unbalansed compare to Raptor Cove on desktop. HCC Sapphire Rapids have 1.875 MiB of L3 per Core and get this 2MiB L2 per core. IT must be the first time an Intel CPU that has more total L2 Cache per CPU than L3.

56C/116T Xeon W9 has 105 MiB of L3 and 112MiB of L2...
 
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nicalandia

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A full unrestrained Raptor Cove vs Genoa Would be an amazing match. 64C/128T With 192 MiB L3. But instead the best Sapphire Rapids will bring 60C/120T with 112 MiB..

Chips and Cheese made Cache System Simulation and Alder Lake gains IPC just by encreasing the shared L3 from 30 MiB to 36 MiB, and that happens to be Raptor Lake.

 
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