"Software" is a pretty vague term here. While the licensing costs are probably eye watering does it include the man hours designing and egnineering your designs?
I obviously didn't make this chart, but based upon the category labels, this should fall under the architecture and verification sections.
With time even those costs will drop, licences are a prime spot for negotiation, using mature third party IP blocks, reusing your own IP blocks
This is true, but it is still true that the IP will almost always cost less on older nodes.
tool development to reduce hours of simulation or automated designing and even open specifications so companies can share costs.
Most companies have moved more away from internal tool development as it becomes too expensive to continue to develop. There will be some small tools that they may use internally, but the major stuff is all handled by 3rd party software and it costs $$$. Open source is not an option here. Design automation is continually being worked on and improving but that still ties back into software/license costs.
A lot of the talk from chip companies moving forward is about how they're compartmentalising their design efforts so a soc can be made in a more mix and match style reducing costs.
This is something AMD has done well, much better and more broadly than Intel, to reduce costs. Just from casual conversations with colleagues, it's being done more and more across the industry.
So a new product on a new node will certainly cost the earth but that can be amortised even early on across multiple products and then the node will mature over time,
This is a big reason why AMD designs 1 CCD and uses it across server, desktop, and workstation. APUs are separate but they try to use the same building blocks inside as much as possible.
see N7 to N6, tsmc themselves say they want people to move to N6 and a good way to that is to offer better value to their customers so I would bet it is significantly cheaper than the day1 N7 ~$300M figure we have for a new design.
I believe N7 design rules are compatible with N6 so you don't have to put in much money to move from one to the other if you don't want to optimize for the new node. You won't really save any design costs going with N6 versus N7 though on a new design. TSMC wants people to move to N6 to save production costs because it requires fewer masks/steps.
Overall, I agree the absolute numbers shown in the graph are more than a bit inflated, as is the % change between the last few nodes, but what is accurate is that it is getting more and more expensive to develop on leading edge nodes, and not in a linear fashion.
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