Discussion Intel current and future Lakes & Rapids thread

[dullard]

So what do you think these N3 wafers were for if it wasn't for Meteor's IGP? Unless you don't believe that Intel had bought N3 wafers for 2H 22/1H 23 period.

Arrow Lake development would be at least part of it. The leaked Intel document shows the Arrow Lake CPU and iGPU on N3 to be 2H22 (B0 and ES1) and 1H23 (for most of the rest of the developmental stages).

I would also assume at least some of their 3rd generation ARC graphics cards would be on N3. But that market cratered with crypto's crash. So, it would be highly likely that Intel scaled back plans (also since it seems like ARC currently sucks).

 

[DrMrLordX]

I've been thinking that Since SPR have been on an Eternal ES Cycle for a few years now. Is Intel actually closer to releasing Emerald Rapids than Sapphire Rapids? Please don't tell it's the same Team working on both, I always thought they had different team working on separate projects....

Others have covered your question quite well, so I'll just add that it seems likely that fixing the UPI bug (or whatever it is that's holding back Sapphire Rapids) will be necessary before Emerald Rapids could be brought to market. In theory, fixing Sapphire Rapids should allow Intel to bring up Emerald Rapids pretty quickly. In practice we'll have to wait and see. Plus Sapphire Rapids is so late that Emerald Rapids probably won't help them much.

 

[shady28]

Well that's a likely possibility in its own right, given that N3 availability de facto starts in 2023.

But to address the broader point, they could have wanted N3 for server (good match for the Forest line in particular), Arrow Lake (as leaked), Lunar Lake (still planned?), and/or dGPUs. If anything, using limited leading node capacity on a mainstream iGPU seems like an incredible waste, wouldn't you agree?

Actually what I think most folks are missing out on is how far behind TSMC is on their original N3 roadmap.

TSMC was supposed to be in full ramp N3 production late 2021. We should have 3nm iPhones coming out in two months, but we don't. And when they do come out in 2023, only the most expensive iPhones will be 3nm. So maybe half of what was originally thought.

Anyway, I think they are in a very slow, slower than originally planned for 2021, late 2022 production run for Apple and Intel, and won't ramp like their original projections until late 2023.

Now this gives Intel and Samsung a reprieve. I don't care for Samsung and its node name hijinx though, their "3nm" node is about like TSMCs enhanced N5 aka N4.

Intel's 4 node is reportedly superior to TSMC N4, so if Intel ships functioning 'Intel 4' node chips in 1H2023 - reality will be that they will have the best x86 node with a shipping product in the consumer space at that time. Might not last long, but it'll be the first time they could say that in over 5 years.

 

[nicalandia]

If MTL will not have a tGPU tile, then so be it and make that CPU a desktop CPU anyways. Let's have Redwood Cove on Desktop by 2023

 

[Hitman928]

"Software" is a pretty vague term here. While the licensing costs are probably eye watering does it include the man hours designing and egnineering your designs?

I obviously didn't make this chart, but based upon the category labels, this should fall under the architecture and verification sections.

With time even those costs will drop, licences are a prime spot for negotiation, using mature third party IP blocks, reusing your own IP blocks

This is true, but it is still true that the IP will almost always cost less on older nodes.

tool development to reduce hours of simulation or automated designing and even open specifications so companies can share costs.

Most companies have moved more away from internal tool development as it becomes too expensive to continue to develop. There will be some small tools that they may use internally, but the major stuff is all handled by 3rd party software and it costs $$$. Open source is not an option here. Design automation is continually being worked on and improving but that still ties back into software/license costs.

A lot of the talk from chip companies moving forward is about how they're compartmentalising their design efforts so a soc can be made in a more mix and match style reducing costs.

This is something AMD has done well, much better and more broadly than Intel, to reduce costs. Just from casual conversations with colleagues, it's being done more and more across the industry.

So a new product on a new node will certainly cost the earth but that can be amortised even early on across multiple products and then the node will mature over time,

This is a big reason why AMD designs 1 CCD and uses it across server, desktop, and workstation. APUs are separate but they try to use the same building blocks inside as much as possible.

see N7 to N6, tsmc themselves say they want people to move to N6 and a good way to that is to offer better value to their customers so I would bet it is significantly cheaper than the day1 N7 ~$300M figure we have for a new design.

I believe N7 design rules are compatible with N6 so you don't have to put in much money to move from one to the other if you don't want to optimize for the new node. You won't really save any design costs going with N6 versus N7 though on a new design. TSMC wants people to move to N6 to save production costs because it requires fewer masks/steps.

Overall, I agree the absolute numbers shown in the graph are more than a bit inflated, as is the % change between the last few nodes, but what is accurate is that it is getting more and more expensive to develop on leading edge nodes, and not in a linear fashion.

 

[Hitman928]

Actually what I think most folks are missing out on is how far behind TSMC is on their original N3 roadmap.

TSMC was supposed to be in full ramp N3 production late 2021. We should have 3nm iPhones coming out in two months, but we don't. And when they do come out in 2023, only the most expensive iPhones will be 3nm. So maybe half of what was originally thought.

Anyway, I think they are in a very slow, slower than originally planned for 2021, late 2022 production run for Apple and Intel, and won't ramp like their original projections until late 2023.

Now this gives Intel and Samsung a reprieve. I don't care for Samsung and its node name hijinx though, their "3nm" node is about like TSMCs enhanced N5 aka N4.

Intel's 4 node is reportedly superior to TSMC N4, so if Intel ships functioning 'Intel 4' node chips in 1H2023 - reality will be that they will have the best x86 node with a shipping product in the consumer space at that time. Might not last long, but it'll be the first time they could say that in over 5 years.

I don't think TSMC ever planned (or at least stated in any of their public roadmaps) to ramp N3 in 2021. The original plan was to ramp N3 in the second half of 2022 which got delayed to first half of 2023. TSMC said they will still get some chips out by the end of 2022 to select customers, but then the real volume will come early 2023.

 

[pakotlar]

So it will be short lived Waste of Sand like Rocket Lake and others in Intel past?

Thats my 5 internet demerits bet yeah

 

[shady28]

I don't think TSMC ever planned (or at least stated in any of their public roadmaps) to ramp N3 in 2021. The original plan was to ramp N3 in the second half of 2022 which got delayed to first half of 2023. TSMC said they will still get some chips out by the end of 2022 to select customers, but then the real volume will come early 2023.

They were supposed to ramp in 2021 and have HVM (high volume) in early 2022. We are looking at 2022/2023 right now.

To be fair, their original original way back in 2019 map had N3 in 2023. Looks like that was the right map.

"Continuing with the goal to match or even beat the famous Moore's Law, TSMC is already planning for future 3 nm node manufacturing, promised to start HVM as soon as 2022 arrives, according to JK Wang, "

TSMC on Track to Deliver 3 nm in 2022

TSMC is delivering record results day after day, with a 5 nm manufacturing process starting High Volume Manufacturing (HVM) in Q2 next year, 7 nm process getting plenty of orders and the fact that TSMC just became the biggest company publicly trading in Asia. Continuing with the goal to match or...

www.techpowerup.com

 

[moinmoin]

"Software" is a pretty vague term here. While the licensing costs are probably eye watering does it include the man hours designing and egnineering your designs?
With time even those costs will drop, licences are a prime spot for negotiation, using mature third party IP blocks, reusing your own IP blocks, tool development to reduce hours of simulation or automated designing and even open specifications so companies can share costs.
A lot of the talk from chip companies moving forward is about how they're compartmentalising their design efforts so a soc can be made in a more mix and match style reducing costs. So a new product on a new node will certainly cost the earth but that can be amortised even early on across multiple products and then the node will mature over time, see N7 to N6, tsmc themselves say they want people to move to N6 and a good way to that is to offer better value to their customers so I would bet it is significantly cheaper than the day1 N7 ~$300M figure we have for a new design.

My understanding is that "software" in this case is to be understood broadly, not only building the models but including processing time spent for physical simulation (= executing the software). The amount of transistors is rising quickly, the amount of layers is also increasing quickly, the mutual interaction of different materials used, increasing leakage etc. pp. are furthermore increasing complexity of the physical simulation.

Considering N6 reduces the amount of layers by replacing several DUV layers in N7 with fewer EUV ones the complexity should be reduced somewhat there as well.

 

[shady28]

My understanding is that "software" in this case is to be understood broadly, not only building the models but including processing time spent for physical simulation (= executing the software). The amount of transistors is rising quickly, the amount of layers is also increasing quickly, the mutual interaction of different materials used, increasing leakage etc. pp. are furthermore increasing complexity of the physical simulation.

Considering N6 reduces the amount of layers by replacing several DUV layers in N7 with fewer EUV ones the complexity should be reduced somewhat there as well.

I actually wasn't really focused on that chart with the big numbers. This is just one part, and yes those graphs are for a new SoC - not porting an existing or mostly existing part or a small part.

What I was really pointing out, is the cost per chip in the other graph. The density roughly doubles each gen there.

In the past, going to a new node has significantly lowered the cost per chip. i.e. going from 90nm to 65nm you double the number of chips per wafer, while the foundry only charges about 15% more per wafer to make. This is why say an i5 today can cost about the same as an i5 from 15 years ago.

Go to the other side of the chart and you can see, 7nm -> 5nm the charge is +82%. So the scaling falls apart right in there, especially if you take into account cost to design too. They'll get hit on both sides.

I may not be 100% on the inflection point, it's going to depend a lot on that other chart and specifics of what the chip is, but we're already near the end of new nodes making economic sense right now IMO.

I see Apple's 2023 "5nm for the proletariat, 3nm for the rich folk" bifurcation to be part of that. There may be a whole lot more segmentation here as we go to 2nm and 18A.

 

[Hitman928]

They were supposed to ramp in 2021 and have HVM (high volume) in early 2022. We are looking at 2022/2023 right now.

To be fair, their original original way back in 2019 map had N3 in 2023. Looks like that was the right map.

"Continuing with the goal to match or even beat the famous Moore's Law, TSMC is already planning for future 3 nm node manufacturing, promised to start HVM as soon as 2022 arrives, according to JK Wang, "

TSMC on Track to Deliver 3 nm in 2022

TSMC is delivering record results day after day, with a 5 nm manufacturing process starting High Volume Manufacturing (HVM) in Q2 next year, 7 nm process getting plenty of orders and the fact that TSMC just became the biggest company publicly trading in Asia. Continuing with the goal to match or...

www.techpowerup.com

2021 was always for risk production. Ramp was second half 2022. https://www.anandtech.com/show/1602...technology-details-full-node-scaling-for-2h22

I think the techpowerup article author misinterpreted what Mr. Wang was saying as they do not provide a direct quote. Barring a direct quote, I would have to side with the official statements the company made as the techpowerup article doesn't mesh with what TSMC was telling everyone else at the time. Just a guess, but Mr. Wang probably said something along the lines of, we will now be able to start volume ramp of N3 as soon as 2022. This statement would make sense because the original projection, as you point out, was for 2023.

Edit:

Actually, it looks like techpowerup was sourcing Digitimes but then adding their own assumptions to it. Their source article doesn't mention or indicate a ramp, "as soon as 2022 arrives" but instead says this:

TSMC is firmly on track to move 5nm process technology to commercial production in the first half of 2020 and will kick off production of chips built using a newer 3nm process node in 2022, according to JK Wang

TSMC to kick off 3nm process manufacturing in 2022

TSMC is firmly on track to move 5nm process technology to commercial production in the first half of 2020 and will kick off production of chips built using a newer 3nm process node in 2022, according to JK Wang, the firm's senior vice president for fab operations.

www.digitimes.com

Tom's hardware also wrote an article on the same material at that time and had no time frame within 2022 in their wording either:

TSMC continues to keep up the pace with its transition to smaller process nodes. According to JK Wang, the company's senior vice president for fab operations, TSMC is on track to start 5nm commercial production in the second half of 2020, while it’s also expected to start 3nm volume production in 2022.

Report: TSMC To Start 3nm Volume Production In 2022

TSMC fab plans are as aggressive as ever.

www.tomshardware.com

So going back to what TSMC actually said, it was H2 2021 for risk production and volume ramp in 2022 which they later specified to be H2 2022. They slipped something like 4 - 6 months.

 

[pakotlar]

More like Trendfarce, amirite?

I appreciate a fine backside myself so…Trendarse

 

[pakotlar]

Old art, but still.........................................

View attachment 65416

Su is such a boss

 

[Exist50]

So it will be short lived Waste of Sand like Rocket Lake and others in Intel past?

Rocket Lake seems like a poor analogy. Raptor Lake or Comet Lake would be better. Emerald Rapids will be clearly better than its predecessor, even if not by nearly enough to close the gap. As for short lived, unfortunately it'll probably be the best Intel can offer for a year.

If MTL will not have a tGPU tile, then so be it and make that CPU a desktop CPU anyways. Let's have Redwood Cove on Desktop by 2023

Likely not possible to swap 1:1 between the two due to IO differences between the two platforms. Even if they do, MTL desktop doesn't seem to be the slightest bit interesting without a noticable improvement from Redwood Cove vs Raptor Cove. 2023 is looking to be a terribly boring year for desktop enthusiasts.

 

[shady28]

Rocket Lake seems like a poor analogy. Raptor Lake or Comet Lake would be better. Emerald Rapids will be clearly better than its predecessor, even if not by nearly enough to close the gap. As for short lived, unfortunately it'll probably be the best Intel can offer for a year.

Likely not possible to swap 1:1 between the two due to IO differences between the two platforms. Even if they do, MTL desktop doesn't seem to be the slightest bit interesting without a noticable improvement from Redwood Cove vs Raptor Cove. 2023 is looking to be a terribly boring year for desktop enthusiasts.

I still think Raptor Lake, being the last monolithic die CPU for consumers, is likely to become a long-living legend and will be top dog in certain workloads for a very very long time. I see it sort of like the transition from big V8s in trucks to little displacement turbo 4 and V6s. Maybe it's a bad analogy, we'll see in time.

 

[Exist50]

I still think Raptor Lake, being the last monolithic die CPU for consumers, is likely to become a long-living legend and will be top dog in certain workloads for a very very long time. I see it sort of like the transition from big V8s in trucks to little displacement turbo 4 and V6s. Maybe it's a bad analogy, we'll see in time.

I doubt it. Ultimately I think the only chiplet tax of note is the penalty to memory latency, but Alder Lake is nothing special in that regard. A gen or two of other improvements should be enough to nullify that even for sensitive code.

 

[IntelUser2000]

It was one of the many "Good Ideas" from their last CEO... Hence he got Fired and I am sure now there is a Non-Rehirable Warning wiht Huge Red Caps on his file.... 😀

I suggest you do a bit more research before commenting anything. Brian Kraznich is a bad CEO but is currently CEO of a company named CDK Global for a few years now.

@Exist50 Rocketlake is not a bad analogy in that it'll be perceived that bad in the market before a big jump occurs which claws back most of the deficit.

 

[nicalandia]

I suggest you do a bit more research before commenting anything. Brian Kraznich is a bad CEO but is currently CEO of a company named CDK Global for a few years now.

So Intel's issues are not due to poor leadership decisions? Who's to blame for this?

 

[IntelUser2000]

So Intel's issues are not due to poor leadership decisions? Who's to blame for this?

I suggest you read my comment again. Of course he is to blame. I call you, Otellini-Kraznich effect!

I doubt it. Ultimately I think the only chiplet tax of note is the penalty to memory latency, but Alder Lake is nothing special in that regard. A gen or two of other improvements should be enough to nullify that even for sensitive code.

Alderlake's high latency might be related to having too many cores on the ring bus. I doubt Raptorlake is better. That's 12 ring stops. Raptorlake needs to do way better just to keep it same as Alderlake. So the ring has a decisive advantage in cache and memory latency(to a lesser degree), which falls as core count grows.

Meteorlake should be much better than both barring a screwup. Even Sapphire Rapids won't be bad.

 

[Exist50]

Alderlake's high latency might be related to having too many cores on the ring bus. I doubt Raptorlake is better. That's 12 ring stops. So the ring has a decisive advantage in cache and memory latency(to a lesser degree), which falls as core count grows.

Meteorlake should be much better than both barring a screwup. Even Sapphire Rapids won't be bad.

Raptor Lake could potentially benefit from higher ring clock speeds from fixing the issue when atom cores are enabled, but if the number of ring stops is the fundamental limitation with memory latency, then it'll only get worse from here. Arrow Lake has 16!

 

[IntelUser2000]

Raptor Lake could potentially benefit from higher ring clock speeds from fixing the issue when atom cores are enabled, but if the number of ring stops is the fundamental limitation with memory latency, then it'll only get worse from here. Arrow Lake has 16!

Actually that's a good point. Does assume they'll stick to the ring with 16 stops though. Past even 10 they used dual stops which really messes with latency and adds complexity.

Raptorlake still needs to counter before getting better. It looks like adding cores brings negatives in a non-linear way. They'll have problems clocking interconnects that high. It likely won't reach 5-plus GHz frequencies of the cores.

 

[Exist50]

Actually that's a good point. Does assume they'll stick to the ring with 16 stops though. Past even 10 they used dual stops which really messes with latency and adds complexity.

They have no choice for anything using the Meteor Lake SoC/topology. No other way to add cores but to extend the ring. Hopefully by Panther or Nova Lake they'll have a more flexible topology.

 

[IntelUser2000]

They have no choice for anything using the Meteor Lake SoC/topology. No other way to add cores but to extend the ring. Hopefully by Panther or Nova Lake they'll have a more flexible topology.

Another way is an octo-core config for the E cores.

 

[jpiniero]

Another way is an octo-core config for the E cores.

That is how I think they will go if they do go 8+32. The Mesh is inevitable though.

 

[Exist50]

Another way is an octo-core config for the E cores.

Even ignoring the question of how the atom modules would scaling in such a config, that wouldn't work for mobile. They're hemmed in on the y dimension.