Discussion Intel current and future Lakes & Rapids thread

[dullard]

The first Athlon 64 X2 CPUs were released in May 2005

https://en.wikipedia.org/wiki/Athlon_64

May 25, 2005 for the Pentium D...

https://en.wikipedia.org/wiki/Pentium_D

And that was the origin of AMD calling intel's chips "glued together".

 

[Markfw]

And that was the origin of AMD calling intel's chips "glued together".

And the AMD X2's were quite a bit faster and ran cooler using less wattage than the Pentium D.

Now lets get back to Intel "something new....."

 

[Thunder 57]

And that was the origin of AMD calling intel's chips "glued together".

Two Pentium 4's connected via FSB, what could possibly go wrong? I guess that is Intel "innovating" though and AMD and Apple just copied it much later on.

 

[dullard]

Two Pentium 4's connected via FSB, what could possibly go wrong? I guess that is Intel "innovating" though and AMD and Apple just copied it much later on.

No, AMD did it independently. Both chips came out about the same time. AMD's implementation was much better and AMD chip sales were deservedly good.

 

[Thunder 57]

No, AMD did it independently. Both chips came out about the same time. AMD's implementation was much better and AMD chip sales were deservedly good.

Sorry, that wasn't meant to be directed at you. I was referring to the original post that was this:

https://twitter.com/x/status/1546242241584173056

intel the innovator.. amd and apple updated it 🙂

K8 was designed to support multicore from the start. Intel got caught with their pants down and had to release something. It was a crappy product that was vastly inferior, but I guess that qualifies as Intel innovating.

 

[Abwx]

And that was the origin of AMD calling intel's chips "glued together".

Actually i had one of those Pentium D, once underclocked it worked well enough without the stock power comsumption, sure that the A64X2 was better but it did cost more than a minimalistic Pentium D 820.

 

[eek2121]

Some folks here were born after the Pentium/Athlon fun. I guess.

Tis a shame. AnandTech even made Star Wars references.

 

[aigomorla]

what is this pentium D you guys are talking about?

You mean that space heater that sat next to your desk to keep your feet warm during winter?

 

[JasonLD]

Lol...

Athlon 64 in September 23, 2003
The first Athlon 64 X2 CPUs were released in May 2005

https://en.wikipedia.org/wiki/Athlon_64

May 25, 2005 for the Pentium D...

https://en.wikipedia.org/wiki/Pentium_D

Well, I am sure the post was about putting more than one chiplet on the package. Not that Pentium D was ever an elegant solution lol.

 

[repoman27]

I'll point out that that article is from quite late '19. Moreover, it sources Digitimes, and while I can't find the full text of the original, they talk about accelerated plans in this article that seems to be the reference. So was the 2023 bit a prediction, or editorialization? https://www.digitimes.com/news/a20191024PD202.html

Additionally, yes, Apple didn't announce their plans till June '20, but rumors proceeded them by quite a while. Additionally, the M1 is basically an A14X. Substitute "Mac chip" with "iPad chip" if you want. Doesn't change the point.

This is kinda getting into the weeds here. The original question we were trying to answer was: what did the Meteor Lake design teams believe about the suitability of N3 back in 2019? There's an obvious distinction between what industry observers might have said, and what TSMC actually shared with customers during that period. During the TSMC Q2 earnings call on July 18, 2019, C. C. Wei stated that:

On N3, the technology development progress is going well, and we are already engaging with the early customers on the technology definition.

I think we can safely assume that the teams at Intel were getting some information directly from TSMC and not just relying on whatever DigiTimes published. The first public statement from TSMC regarding N3 timelines came during the Q1 earnings call on April 16, 2020:

Our N3 technology development is on track, with risk production scheduled in 2021 and target volume production in second half of 2022.

In the absence of clear evidence that TSMC told customers something materially different during the prior 12 months, I tend to believe that Intel was working with accurate information.

As far as Apple goes, they're even more up in TSMC's business, so I don't for a minute believe that they ever targeted N3 for any SoC that was intended to ship in 2022. And yes, anyone paying attention knew that Apple was going to bail on Intel at some point—by early 2018 I was already convinced that it was imperative for Apple to pursue their own SoCs for the Mac line.

However, if you look instead at what industry observers were saying in 2019, you'll find that some believed N3 would trail N5 by three years, and others thought the gap would only be two years. The fact that the editorializations around that time often don't line up with the sources being cited is evidence of that. Once TSMC announced that the target was H2'22, some believed this was pulling the node back in by 6 months or more, while others claimed it was arriving later than expected. Most people have no idea what Apple's production timelines look like, so they saw volume production in 2022 and just assumed the SoC for the 2022 iPhones would be manufactured on N3. Many of those who did understand the implications of H2 but were bullish on TSMC thought that surely TSMC would be able to deliver N3 a quarter or more ahead of schedule in order to accommodate Apple. @Doug S here still thinks there's a possibility that Apple used N3 risk starts to fabricate the A16.

Professional analysts continue to act confused by the H2'22 timeline. From the Q2 2021 earnings call:

Andrew Lu - Sinolink Securities Co., Ltd., Research Division - Semiconductor Analyst
Okay. My first question is regarding 3-nanometer ramp-up for second half, starting from second half next year. I recall the 7-nanometer ramp-up in year 2018 second quarter with some revenue contribution and the 5-nanometer in second quarter last year, year 2020. But it seems like 3-nanometers clearly some delay for second half next year. So I want to ask, is that because the technology difficulty, we cannot ramp up in second quarter or we don't have a big customer to use 3-nanometer at the beginning stage that's why we push back the ramp-up in second half next year? That's my first question.

Jeff Su - Taiwan Semiconductor Manufacturing Company Limited - Director of IR
Okay. So Andrew's first question, let me summarize, is asking about our 3-nanometer ramp. He notes that 5-nanometer and 7-nanometer in the past few years basically ramped in the middle of the year. N3, we said the ramp will be in second half of next year. So what is the reason behind this?

C. C. Wei - Taiwan Semiconductor Manufacturing Company Limited - CEO
Andrew, you have a very good observation and you calculate that, yes, about 3 to 4 months is a delay as compared with 5-nanometer. Yes, 3-nanometer technology actually is very complicated and in both processing technology and also the customers' product design. So we work with a customer, and finally, we decided to ramp up in the second half of next year. And this is -- we decided with our customer with the best fit their need.

Despite 5 quarters worth of consistent communication from TSMC, @witeken promptly latched onto the word "delay", claiming this was somehow a deviation from the public roadmap, and subsequently doubled down on it. Incidentally, you can also check out the editorialization from his own take on the IThome piece that he did for Tom's Hardware.

 

[DrMrLordX]

what is this pentium D you guys are talking about?

You mean that space heater that sat next to your desk to keep your feet warm during winter?

LOL who remembers the watercooled Pentium D 820 article? I don't remember who ran that - I think it was Tom's? - but the crux was that you could be somewhat competitive with a much-more-expensive X2 machine if all you did was rig up a Pentium D 820 with watercooling and ignore the massive power draw. Which kind of worked?

Anyway it was funny.

 

[yuri69]

what is this pentium D you guys are talking about?

You mean that space heater that sat next to your desk to keep your feet warm during winter?

It's kinda funny. That Pentium D 820 got 95W TDP. Current 12900KS got 150-240W TDP.

The Pentium was very mild compared to current heater technology.

 

[IntelUser2000]

Meteorlake should still be on Intel 4. I am expecting similar to Broadwell launch where Core M launched ahead of the rest and with Meteorlake we should see 5W chips. Broadwell's problem was the result of issues with 14nm process. The process seems to be in good condition but based on what's out there they are probably having problems on the packaging and tile integration. The approach is a huge step for the company because now you need to have multiple designs executed flawlessly. While it may seem like it allows for faster reiterations, that's only when everything is firing on all cylinders.

Overall volume might be ending up lower in the same year because we might see most at end of the year or early next year. U9-15, P/H all of them. Maybe they even cut lines entirely to speed up the successor.

It's kinda funny. That Pentium D 820 got 95W TDP. Current 12900KS got 150-240W TDP.

The Pentium was very mild compared to current heater technology.

Not exactly comparable. The highest performing heatsinks back then were the size of SFF heatsinks today. It's absolutely monstrous nowadays and watercooling is very common. The design advanced as well. The cheapie ones are good as the best back then. It's a big part why we are pushing greater than 5GHz clocks.

Turin and even Granite Rapids should push half a kilowatt. HPC GPUs are going to exceed a full kilowatt. Consumer GPUs are going to 400W common. Eventually this 250W barrier on CPUs will be breached too.

The dynamic range continues to expand. That's the best indicator of advancement in all areas.

 

[jpiniero]

There's a practical limit of 1500 W for all but like HPC.

 

[lobz]

This is kinda getting into the weeds here. The original question we were trying to answer was: what did the Meteor Lake design teams believe about the suitability of N3 back in 2019? There's an obvious distinction between what industry observers might have said, and what TSMC actually shared with customers during that period. During the TSMC Q2 earnings call on July 18, 2019, C. C. Wei stated that:

I think we can safely assume that the teams at Intel were getting some information directly from TSMC and not just relying on whatever DigiTimes published. The first public statement from TSMC regarding N3 timelines came during the Q1 earnings call on April 16, 2020:

In the absence of clear evidence that TSMC told customers something materially different during the prior 12 months, I tend to believe that Intel was working with accurate information.

As far as Apple goes, they're even more up in TSMC's business, so I don't for a minute believe that they ever targeted N3 for any SoC that was intended to ship in 2022. And yes, anyone paying attention knew that Apple was going to bail on Intel at some point—by early 2018 I was already convinced that it was imperative for Apple to pursue their own SoCs for the Mac line.

However, if you look instead at what industry observers were saying in 2019, you'll find that some believed N3 would trail N5 by three years, and others thought the gap would only be two years. The fact that the editorializations around that time often don't line up with the sources being cited is evidence of that. Once TSMC announced that the target was H2'22, some believed this was pulling the node back in by 6 months or more, while others claimed it was arriving later than expected. Most people have no idea what Apple's production timelines look like, so they saw volume production in 2022 and just assumed the SoC for the 2022 iPhones would be manufactured on N3. Many of those who did understand the implications of H2 but were bullish on TSMC thought that surely TSMC would be able to deliver N3 a quarter or more ahead of schedule in order to accommodate Apple. @Doug S here still thinks there's a possibility that Apple used N3 risk starts to fabricate the A16.

Professional analysts continue to act confused by the H2'22 timeline. From the Q2 2021 earnings call:

Despite 5 quarters worth of consistent communication from TSMC, @witeken promptly latched onto the word "delay", claiming this was somehow a deviation from the public roadmap, and subsequently doubled down on it. Incidentally, you can also check out the editorialization from his own take on the IThome piece that he did for Tom's Hardware.

witeken and tom's hardware, a match made in heaven

 

[repoman27]

There's a practical limit of 1500 W for all but like HPC.

Well, if you want to sell to consumers in both the US and Japan, 1200 W is a more realistic limit (12 A @ 100 V for 1200 W continuous power). But it's pretty stupid for a single device to pull that much juice, because there's no chance that it will be the only thing that the typical end user plugs into a 15A branch circuit.

 

[nicalandia]

Is this due to bad drivers? So far Sapphire Rapids have been matched against Rome based EPYC and Skylake Xeons and not performing as expected

Intel Sapphire Rapids-SP Xeon Platinum 8480+ 56 Core & Platinum 8450H 28 Core CPUs Tested In Quad-Socket Sever

Intel's Sapphire Rapids-SP Xeon Platinum CPUs have been tested in a quad-socket configuration, offering up to 224 cores & 448 threads.

wccftech.com

 

[pakotlar]

Is this due to bad drivers? So far Sapphire Rapids have been matched against Rome based EPYC and Skylake Xeons and not performing as expected

Intel Sapphire Rapids-SP Xeon Platinum 8480+ 56 Core & Platinum 8450H 28 Core CPUs Tested In Quad-Socket Sever

Intel's Sapphire Rapids-SP Xeon Platinum CPUs have been tested in a quad-socket configuration, offering up to 224 cores & 448 threads.

wccftech.com

View attachment 64453

Yeah hopefully something up with preproduction hardware, or benches chosen that are not representative. Would be very disappointing for 56 core sapphire rapids to lose to 64 core Milan at 50% more power, because it will get slaughtered by Genoa if so.

Or maybe this is real and the HBM version will do better.

 

[nicalandia]

Yeah hopefully something up with preproduction hardware, or benches chosen that are not representative. Would be very disappointing for 56 core sapphire rapids to lose to 64 core Milan at 50% more power, because it will get slaughtered by Genoa if so.

Or maybe this is real and the HBM version will do better.

It's not losing to Milan, but to Rome on many tests. I believe the dreaded Mesh of Rings that is taking out many of the IPC gains, plus the slow clocks.

 

[pakotlar]

It's not losing to Milan, but to Rome on many tests. I believe the dreaded Mesh of Rings that is taking out many of the IPC gains, plus the slow clocks.

Oh that’s bad.

 

[lobz]

I wouldn't read too much into this, in fact, I wouldn't read anything at all into testing with sandra, might as well just read userbenchmark editorials.

 

[nicalandia]

I wouldn't read too much into this, in fact, I wouldn't read anything at all into testing with sandra, might as well just read userbenchmark editorials.

There have been multiple leaks Sapphire Rapids(ES and early samples) struggling with Rome based EPYCs with other benchmark apps like Cinebench R23

I am waiting on the Yuuki_AnS dude to put new benches with QS samples Against ES Genoa and see a more realistic test closer to release samples.

https://twitter.com/x/status/1546658526847647744

 

[DrMrLordX]

It's not losing to Milan, but to Rome on many tests. I believe the dreaded Mesh of Rings that is taking out many of the IPC gains, plus the slow clocks.

Could be where the 2023 delay rumour came from. Someone at Intel has to be at least considering the delay if Sapphire Rapids winds up being not much faster than IceLake-SP due to interconnect (or something else entirely).

 

[moinmoin]

Maybe those are just Sapphire Rapids samples which are not completely unlocked (i.e. performance limited through SDSi). So essentially driver problems. Intel currently likes to invite those.

 

[nicalandia]

Maybe those are just Sapphire Rapids samples which are not completely unlocked (i.e. performance limited through SDSi). So essentially driver problems. Intel currently likes to invite those.

Those are QS Samples with full retail number. Do you think they would be locking those just before the release?(according to Yuuki_AnS the QS don't have SDSi locks)



A pair of Xeon Platinum 8470 52-core /104-thread 2.00 Ghz Base and 3.00GHz Boost TDP350W Is losing to a pair of Rome based EPYC on Cinebench R23?

Cinebench R23 MT 2S System

CineBench R23: 79,150 points
Cinebench R20: 29,344 points