If you want new, wait for Lion Cove. Though Redwood Cove should have more changes than Raptor Cove.
| process | reported EUV layers | max EUV layers | capacity (KWSPM) | EUV systems required | EUV systems installed |
|---|---|---|---|---|---|
| Intel 4 | 12-13 | 13 | 30 | 9 | 12-20 |
| TSMC N7+ | 4 | 4 | 30 | 3 | |
| TSMC N6 | 5 | 5 | 40 | 5 | |
| TSMC N5 | 11-14 | 14 | 100 | 32 | |
| TSMC N4 | 14-15 | 15 | 60 | 20 | |
| TSMC N3 | 20-25 | 25 | 90 | 50 | |
| TSMC total | 110 | 84-115 |
| MTL tile | x (mm) | y (mm) | area (mm²) | dies per wafer | process | defects / cm² | yield (Seeds model) | dies required (M) | wafers required (K) | production quarters | KWSPM required |
|---|---|---|---|---|---|---|---|---|---|---|---|
| 2+8 CPU | 5.1 | 7.9 | 40.29 | 1578 | Intel 4 | 0.20 | 92.54% | 70 | 48 | 0.5 | 32 |
| 6+8 CPU | 8.8 | 7.9 | 69.52 | 909 | Intel 4 | 0.20 | 87.79% | 100 | 126 | 1.5 | 28 |
| 8+16 CPU | 13.9 | 7.9 | 109.81 | 565 | Intel 4 | 0.20 | 81.99% | 80 | 173 | 2 | 29 |
| GT2 GPU | 2.2 | 10.5 | 23.10 | 2708 | TSMC N3 | 0.10 | 97.74% | 170 | 65 | 1 | 22 |
| SoC-LP | 9.0 | 10.5 | 94.50 | 662 | TSMC N6/N5P/N4 | 0.08 | 92.97% | 170 | 277 | 2 | 47 |
| IOE | 5.1 | 2.0 | 10.20 | 6199 | TSMC N6/N5P/N4 | 0.08 | 99.19% | 170 | 28 | 1 | 10 |
| SoC-HP | ? | ? | ~94.50 | 662 | TSMC N6/N5P/N4 | 0.08 | 92.97% | 80 | 131 | 1 | 44 |
| Base-U | 16.9 | 10.85 | 183.37 | 332 | Intel ? | 0.08 | 87.21% | 70 | 243 | 1 | 81 |
| Base-P/H | 20.6 | 10.85 | 223.51 | 269 | Intel ? | 0.08 | 84.83% | 100 | 439 | 1.5 | 98 |
| Base-HX/S | 23.5 | 10.85 | 254.98 | 234 | Intel ? | 0.08 | 83.06% | 80 | 413 | 1.5 | 92 |
| Intel 4 total | 347 | 4 | 29 | ||||||||
| Intel ? total | 1095 | 4 | 92 | ||||||||
| TSMC N3 total | 65 | 1 | 22 | ||||||||
| TSMC N6/N5P/N4 total | 436 | 4 | 37 |
🤔
So Intel has twice as many EUV systems as they need, and D1X Mod 3 alone has the capacity to produce as many Meteor Lake compute tiles as they can possibly sell in a year.
TSMC on the other hand can probably use every EUV system they can get their hands on. N3 seems to have plenty of capacity available though, so TSMC shouldn't have any issue filling orders for MTL GPU tiles. Assuming the HP SoC is roughly the same size as the LP (after adding a GT1 GPU and moving the PCH stuff to a separate chip), the SoC tiles are going to require a fair number of wafer starts. I don't think TSMC has enough N6 capacity to accommodate a full Meteor Lake stack. So either Intel is planning lower volumes for MTL and counting on RPL to pick up the slack, or at least the SoC-LP tile is on an N5 family process.
I don't know where Intel is making the interposers, but that is a *lot* of wafers if they go all-in on tiled platforms for the client group.
I doubt Intel 7 right now is even close to 0.2. Let alone Intel 4, who knows what that would be.
I am guessing that required number of EUV machines for 30kwpm is also far too low.
I am guessing that required number of EUV machines for 30kwpm is also far too low.
Numbers are Up for Sapphire Rapids QS sample and AMD Genoa ES sample for CineBench. Thanks to YuuKi_AnS
For some reason Cinebench is not detecting the full 196 Cores of Genoa so it's only working with 128C/256T and even with that it's breaking the 100,000 points. It would be close to 150,000 with 192 cores.
For some reason Cinebench is not detecting the full 196 Cores of Genoa so it's only working with 128C/256T and even with that it's breaking the 100,000 points. It would be close to 150,000 with 192 cores.
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Seriously? Where do you think D0 for Intel 7 is at right now? And my numbers are based on what we might expect when those dies reach HVM, not where the process was at any point during pre-production.
And as usual, my numbers are based on what ASML has told us: 1 EUV layer requires 1 EUV system for every 45k wafer starts per month. Not sure why people keep arguing with this number when it comes to Intel. You can also go by the specs for the individual systems. The NXE:3400C/D are good for 135-170 wph. Even at 135 wph, 45 kwspm only represents a 46.3% duty cycle.
Lets say 0.5. Which is perfectly fine for tiny client parts where it's OK if half the chip is busted.
Expecting Intel to be that productive with the production R&D fab is rather optimistic. And Intel normally likes to have multiple production lines at multiple sites ready to go at HVM - 10 nm did originally.
I will say that the CPU only tiles should be very salvageable. I almost wonder if the issue is that they realized that selling Celerons with $50 worth of TSMC is not a good idea.
WCCFTECH is out with the Leak by YuuKi_AnS
wccftech.com
There are just too many inconsistencies on those charts.
at least one of those 8480 is a QS sample(the 8480+), but both of those 8480 should have 60C/112T or 120 cores on a 2S system. YuuKi_AnS have been posting performance on many early SPR based Xeons samples and even the best score so far posted was 79,000 points on CB R23. That was a 2S System with two QS grade 8470 CPU.
Too early to test a SPR vs Genoa at this stage. Buggy Bios(By both companies and Genoa is not supported by Windows Server 2022 so a early sample of 2025 Windows Server was used)
AMD EPYC Genoa With 96 Zen 4 Cores Is An Insanely Fast Chip, Crushes Every Other x86 Processor In Leaked Benchmarks
The latest benchmarks of AMD's upcoming EPYC Genoa 96 Core CPU based on the Zen 4 core architecture have been leaked.
wccftech.com
There are just too many inconsistencies on those charts.
at least one of those 8480 is a QS sample(the 8480+), but both of those 8480 should have 60C/112T or 120 cores on a 2S system. YuuKi_AnS have been posting performance on many early SPR based Xeons samples and even the best score so far posted was 79,000 points on CB R23. That was a 2S System with two QS grade 8470 CPU.
Too early to test a SPR vs Genoa at this stage. Buggy Bios(By both companies and Genoa is not supported by Windows Server 2022 so a early sample of 2025 Windows Server was used)
Gaming Benchmarks are in..
It's about 5% performance boost in gaming(due to higher clocks) than 12900K, But it consumes 53% more power than the 12900K
Intel Core i9-13900K Raptor Lake CPU Gaming & Synthetic Performance Benchmarks Leaked, 5% Faster Than Core i9-12900K On Average
The first gaming and synthetic performance benchmarks of Intel's Core i9-13900K Raptor Lake 5.5 GHz CPU have been leaked.
It sounds like another 12900KS and it will be a gaming match with the 5800X3D....
UP TO 50% more power. On average 20%. Still, not an amazing showing.
It's also worth nothing that the graph is title "Peak Power Consumption", so it may very well be +20% peak on average...which doesn't really mean much.
You realize that Intel 7 is 10nm, which has been in HVM for three full years at this point? So you think the D0 for Intel 7 is still higher than it was for any of TSMC's recent nodes three quarters prior to volume production? And you think Intel is still averaging over 350 defects per wafer? OK.
D1X is currently Intel's largest fab. Mods 1 and 2 are each the same size as Fab 42 in AZ, and Mod 3 is even bigger with 270,000 square feet of clean room space. So yeah, 30 kwspm should be no problem whatsoever. The problem is that Intel couldn't even sell their own teams on Intel 4, so they have very few things in need of manufacturing on that node. Fab 34 in Leixlip will come online in 2023 as the second production site for Intel 3/4.
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Meteor lake for mobile and desktop is most interesting for me.. will be intel's first euv node the performance per watt should be great 🤔
poke01
Diamond Member
- Mar 8, 2022
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Yes MTL is on Intel 4 and if even if Intel push the CPU power at the same TDP (Like say 65 W RPL to 65 W MTL), MTL should be way more power efficient. I believe Intel won't push high TDP on the i3, i5, i7 and even on the i9 I expect the TDP and peak power to get reduced. Intel cannot always "push" the chips because 99.999% of people don't cool their CPUs using liquid nitrogen.
TL;DR: MTL should offer much better Pref/w being on Intel 4 and EUV based. The future of CPUs leadership will be efficiency and pref/w and AMD on x86 land leads on that. That is why Intel's future Lakes needs to be focused on efficiency and its crucial.
Yeah it seems its going to take Intel a while to have an unambiguously superior CPU. The good news is that their current stuff isn’t bad, the industry is just far more mature, better competition. I’m all for AMD and Intel pushing each other to new heights.
DrMrLordX
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I believe the expectation was that nobody could show any evidence that ASML had delivered enough EUV equipment to Intel to sustain those production levels (estimated production levels were 20 kwpm). Though we may be measuring something differently here.
In any case I had expected a dearth of Intel 4 products for that reason - insufficient wafer output due to machinery shortages. In a way, it's kind of worse if their own teams simply don't want anything to do with the node.
It has Sapphire Rapids numbers.
moinmoin
Diamond Member
- Jun 1, 2017
- 5,247
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Yes really, ADL introduced E cores but brute forces inefficient peak performance out of them. I'd expect ADL+1 to balance that more both in hardware and software, especially since it adds even more E cores. The very fact that power consumption is rising further tells me Intel didn't deem such an approach low hanging fruits which is disappointing to say the least.
Based upon Intel's financial statements, Intel was "losing money" (eg: including the depreciation) on anything 10 nm up to and past the Tiger Lake launch. Back then they were probably throwing away a large portion of the wafer getting nothing. Wasn't until Q1 21 if I remember that they were getting enough chips to stop losing money. You can see why they were having serious internal discussions about whether to move forward with a future node... until Pat got the bright idea to con Governments to pay for it.
The main difference is that capacity was never an issue with 10 nm. It was always about the yields.
MTL is bigger change than RPL for sure, but i'm more excited for Zen 5 which will be new grounds-up architecture coupled with Xilinx AI accelerators, AMD saved most resources for Zen 5, while only small team worked on Zen 4 because RPL is just refresh of ADL so they don't need to spend too much money on that.
My table uses the same Mizuho Securities data that led most of the internet to assume that Intel was capacity constrained due to lack of EUV systems. I just chose not to badly misinterpret that data. Mizuho did indeed forecast 20 kwspm for Intel 4 in 2023, but that was in no way related to the number of EUV systems they expected them to have. Anyone who bothered to do the math or look at Intel's roadmap could see that.
Mizuho stated that Intel took delivery of 10 EUV systems between 2018-2020, and estimated that they would receive an additional 2 in 2021 with 3 more coming in 2022. I assumed that systems delivered in 2021 would likely be installed by the end of this year, but the 2022 deliveries probably couldn't be counted on until late 2023. We also know that ASML shipped 25 EUV systems prior to 2018 and that TSMC received 15 of those. It is plausible that Intel received up to half of the remaining 10 systems shipped during that period. That works out to a range of 12 to 20 EUV systems available to Intel during the next four quarters.
I then checked Mizuho's capacity forcasts for 2023 to see how many EUV systems Intel and TSMC would actually need. I deliberately bumped Intel 4 up to 30 kwspm to show that they have more than enough EUV systems to handle any capacity they could conceivably use, and because D1X Mod3 alone can accommodate at least 30 kwspm. I also reduced Mizuho's TSMC N3 estimate down to 90 kwspm from 120 because we know they only have three fabs available for N3 after the N5 expansion took over Fab 18 phase 4, and initial volume for phases 5 and 6 is only 30 kwspm. I applied the same "1 EUV system per EUV layer for every 45 kwspm" rule to every node using the maximum reported number of EUV layers to ensure sufficient capacity.
I'm introducing very little additional information that was not available back in April, 2021 when the Mizuho guidance for ASML was published. The evidence was sitting there the whole time; people just love rumors and hate math.
DrMrLordX
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It was a realistic and likely quite accurate estimate of Intel's actual utilization of that node. The entire point of including that table in a buy rating for ASML was to project demand for both DUV and EUV equipment coming from ASML's top three customers. It was *never* meant as an indictment of Intel's EUV strategy. It was for investors to see where future demand for ASML's products would be coming from based on customer roadmaps and other available data.
So to reiterate, I increased the capacity for Intel's only EUV node by 50%, and reduced capacity for TSMC's most EUV intensive node by 25%, and Mizuho's numbers still show TSMC as being constrained and Intel having a surplus of EUV systems. If we look at wafers per month per EUV system using Mizuho's numbers, Intel's systems would need to process fewer than 22 kwpm, whereas meeting TSMC's capacity numbers would require their systems to process at least 41 kwpm or potentially as many as 67 kwpm (which is not happening). So if Mizuho wasn't basing TSMC's capacity forecast on availability of EUV systems, why would they have done so for Intel?
Intel did mention this months ago. People here just chose not to believe them for whatever reason.
The *mont cores have so much potential. Too bad Intel is squandering it in the desire to beat AMD at all costs.
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