Aapje
Golden Member
- Mar 21, 2022
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Well since ARC is being made by TSMC, does this mean Intel are going to give their underused EUV machines to TSMC?
Aapje
Golden Member
- Mar 21, 2022
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As was my reply.
Even if they are not using or able to use them, Intel are not going to give away or sell their scares EUV machines if only to deny them to others!
IntelUser2000
Elite Member
- Oct 14, 2003
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Hence the term perma-bears. We have two here. In the beginning of Tigerlake there was some merit but now it's just refusing to accept the change.
It can be argued whether they are pushing it so much but losing in performance is generally a bad thing for perception. The halo SKUs not only command a much higher revenue and profit margin, but it affects sales of the generation as a whole. If your halo chip loses to the competition, it's really a second place chip and not a true halo. Difference between 350 vs 500 dollars.
poke01
Diamond Member
- Mar 8, 2022
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ADL and RPL uses the same e cores, Gracemont and its not until Meteor Lake we see new e cores(Crestmont). The e cores on RPL will double and provide extra MT Intel wants.
The cache size increases for the RPL e-cores alone means it's not exactly the same chip as the one on ADL. What remains to be seen is whether there's going to be clock regressions on the e-cores or not.
DrMrLordX
Lifer
- Apr 27, 2000
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It appeared as though they were. As you said, it was basically an ad for ASML, showing that every major foundry player would be constrained by EUV equipment in the near future.
It's a little hard to believe them these days.
poke01
Diamond Member
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What I meant was the micro-architecture the cores are based on. ADL and RPL use Gracemont but RPL has largely the same e-cores as ADL.
As for P-cores that is Raptor Cove we may see bigger changes there.
Intel Sapphire Rapids QS E3 Sample. Production performance numbers. That CPU is as close as anyone will get to a production CPU for performance(But the Bios is still Beta)
More info on them.
84080+ is the QS E3 sample on a 2S System
Those L3 numbers are downright painful compared to Genoa, nevermind Genoa-X. No wonder they need the HBM version to compete.
Well, it was indeed an ad for ASML stock, but the headline wasn't, "This one company is holding back the entire leading-edge semiconductor industry: Strong Buy". I think the idea was that demand for EUV systems was clearly trending upwards, and despite orders being fully booked two years out, ASML would be able to hit their delivery schedule and meet demand going forward. I'm sure Mizuho never meant to suggest that ASML would be capacity constrained to the point of negatively impacting their customers' business.
I'm pretty sure it was Daniel Nenni over at SemiWiki who first floated the idea that the Mizuho report indicated that Intel's upcoming node was going to be capacity constrained due to EUV system availability.
It's actually a bizarre takeaway, not at all supported by the numbers, and super TSMC biased.
I updated these to reflect the increased N6 capacity outlined by TSMC during their 2021 Technology Symposium, and I revised Intel 4 capacity upwards again to accommodate a D0 of 0.5 as proposed by @jpiniero.
Intel still has enough EUV systems and cleanroom space at D1X to produce 250 million Meteor Lake compute tiles.
TSMC capacity is at the upper end of the range based on installed EUV systems. Producing all of the MTL SoC tiles on N6 would utilize nearly half of TSMC's total capacity on that node for a full 4 quarters. I'm guessing there are too many other customers on N6 for TSMC to agree to that, so either the planned volumes for MTL are significantly lower, the SoC-LP is on an N5 family process, or the SoC-HP is being manufactured by Samsung.
| process | reported EUV layers | max EUV layers | capacity (KWSPM) | EUV systems required | EUV systems installed |
|---|---|---|---|---|---|
| Intel 4 | 12-13 | 13 | 40 | 12 | 12-20 |
| TSMC N7+ | 4 | 4 | 30 | 3 | |
| TSMC N6 | 5 | 5 | 80 | 9 | |
| TSMC N5 | 11-14 | 14 | 100 | 32 | |
| TSMC N4 | 14-15 | 15 | 60 | 20 | |
| TSMC N3 | 20-25 | 25 | 90 | 50 | |
| TSMC total | 114 | 84-115 |
| MTL tile | x (mm) | y (mm) | area (mm²) | dies per wafer | process | defects / cm² | yield (Seeds model) | dies required (M) | wafers required (K) | production quarters | KWSPM required |
|---|---|---|---|---|---|---|---|---|---|---|---|
| 2+8 CPU | 5.1 | 7.9 | 40.29 | 1578 | Intel 4 | 0.50 | 82.23% | 70 | 54 | 0.5 | 36 |
| 6+8 CPU | 8.8 | 7.9 | 69.52 | 909 | Intel 4 | 0.50 | 74.21% | 100 | 149 | 1.5 | 34 |
| 8+16 CPU | 13.9 | 7.9 | 109.81 | 565 | Intel 4 | 0.50 | 64.56% | 80 | 220 | 2 | 37 |
| GT2 GPU | 2.2 | 10.5 | 23.10 | 2708 | TSMC N3 | 0.10 | 97.74% | 170 | 65 | 1 | 22 |
| SoC-LP | 9.0 | 10.5 | 94.50 | 662 | TSMC N6/N5P/N4 | 0.08 | 92.97% | 170 | 277 | 2 | 47 |
| IOE | 5.1 | 2.0 | 10.20 | 6199 | TSMC N6/N5P/N4 | 0.08 | 99.19% | 170 | 28 | 1 | 10 |
| SoC-HP | ? | ? | ~94.50 | 662 | TSMC N6/N5P/N4 | 0.08 | 92.97% | 80 | 131 | 1 | 44 |
| Base-U | 16.9 | 10.85 | 183.37 | 332 | Intel ? | 0.08 | 87.21% | 70 | 243 | 1 | 81 |
| Base-P/H | 20.6 | 10.85 | 223.51 | 269 | Intel ? | 0.08 | 84.83% | 100 | 439 | 1.5 | 98 |
| Base-HX/S | 23.5 | 10.85 | 254.98 | 234 | Intel ? | 0.08 | 83.06% | 80 | 413 | 1.5 | 92 |
| Intel 4 total | 423 | 4 | 36 | ||||||||
| Intel ? total | 1095 | 4 | 92 | ||||||||
| TSMC N3 total | 65 | 1 | 22 | ||||||||
| TSMC N6/N5P/N4 total | 436 | 4 | 37 |
Intel still has enough EUV systems and cleanroom space at D1X to produce 250 million Meteor Lake compute tiles.
TSMC capacity is at the upper end of the range based on installed EUV systems. Producing all of the MTL SoC tiles on N6 would utilize nearly half of TSMC's total capacity on that node for a full 4 quarters. I'm guessing there are too many other customers on N6 for TSMC to agree to that, so either the planned volumes for MTL are significantly lower, the SoC-LP is on an N5 family process, or the SoC-HP is being manufactured by Samsung.
I said I was suggesting Intel 7 is around 0.5. I have no idea what Intel 4 is expected to be in 2023, it could be 20 for all I know.
Your own estimate says they would need 423k wafers (a year?) when they would maybe in theory be able to do 120.
Good news is that your estimate of 250 M dies for a year needed is also far too high. It's not like 100% of Intel's sales are ever of the latest generation.
Your own estimate says they would need 423k wafers (a year?) when they would maybe in theory be able to do 120.
Good news is that your estimate of 250 M dies for a year needed is also far too high. It's not like 100% of Intel's sales are ever of the latest generation.
Why would you expect defect densities on Intel 4 to be higher than 0.5? SAQP has been mostly eliminated, pure cobalt is out, enhanced copper is in... Or is it just that you have zero confidence in Intel and are making these numbers up without considering any of the available data?
423,000 wafers in total, manufactured during the span of 4 quarters. Which works out to 35,250 wafers per month, which Intel is entirely capable of. They currently have enough EUV systems and fab space for 40,000 wafer starts per month.
What exactly is your "theory" of why Intel can only manage 10 kwspm?
Exactly. Intel will be lucky to sell 250M client platforms in 2023, and there is no chance that they would be 100% Meteor Lake. As usual, the product mix will include a hefty percentage of salvaged dies that are partially or mostly disabled. My yield calculations are only to eliminate unsalvageable dies and don't address parametric yields or binning. So using your preposterously high D0 numbers just further drives home the point—Intel 4 is in no way capacity constrained.
Those TSMC numbers are likely to be pretty close to accurate since you'd have to assume that given they've been able to sell everything they can make they'd want to be using all their EUV systems in production, other than a few piloting future node development like N2 and beyond. There will not have EUV systems sitting idle, and are able to make immediate (well "immediate" after the months of installation/calibration time) use of every new delivery to beef up existing capacity. Starting in 2024 all their deliveries will presumably go to building N2 lines.
Intel's number seem reasonable to be me as well, since even if they sold/traded some of their orders to TSMC in exchange for N3 capacity their long delay getting 10nm / Intel 7 to work meant 7nm / Intel 4 production is happening several years later than originally planned. So if anyone has EUV scanners sitting around unused, it is going to be Intel. I can't imagine EUV scanners are going to be a limiter for them when they are only now ramping up their first process that uses them.
Intel's number seem reasonable to be me as well, since even if they sold/traded some of their orders to TSMC in exchange for N3 capacity their long delay getting 10nm / Intel 7 to work meant 7nm / Intel 4 production is happening several years later than originally planned. So if anyone has EUV scanners sitting around unused, it is going to be Intel. I can't imagine EUV scanners are going to be a limiter for them when they are only now ramping up their first process that uses them.
You mean besides that they've delayed the node multiple times already, and ate a substantial amount of money on Ponte Vecchio? Plus this rumored meeting that Pat is going to TSMC about trying to weasel out of their Meteor Lake SoC/IGP obligations because of Intel 4 problems?
IMO Intel will announce another Intel 4 delay soon. Just have to wait until there's clarity on whether the chips bill is going to pass or not.
That's basically what Digitimes was implying. You can choose not to believe it. The alternative is that they would build the CPU tile at TSMC as well, but the timing doesn't seem to support it unless they've already started.
No, that simply wasn't part of it at all. They claimed that because of Intel's schedule slip, they want to negotiate more/later N3 wafers to avoid penalties from breaking their agreement. Nothing at all about needing more N3 because of Intel 4 issues.
Why invent your own rumor and attribute it to someone else? Intel 4 could even be delayed and it still wouldn't change what digitimes said.
shady28
Platinum Member
- Apr 11, 2004
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This is based on ASML Financial reporting, # of EUV systems per year :
| 2015-2017 | 16 | |
| 2018 | 18 | |
| 2019 | 26 | TSMC has half of all EUV machines (statement in Aug 2020) = 30 |
| 2020 | 31 | |
| 2021 | 32 | Based on 2x first half 2021 |
| Total | 123 |
Even if TSMC had bought every single EUV machine after their statement in 2020 of having half of the ones made to that point, they'd still only have about 90. A lot more likely they have about 60-70 right now. The earlier machines cannot do below 5nm (TSMC N7/N5/N4).
TSMC would need a 3600D for 3nm, and ASML delivered its first one in mid 2021. Earlier models were 7 / 5nm (TSMC N7 / N5 / N4).
Intel also purchased a number of these earlier units and reported have at least a couple of them up and running in 2019, but yields were not as good as expected. In 2015 Intel had ordered 15 EUV systems from ASML, which is half of what was produced up until 2019.
If we assume ASML is producing the 3600D as fast as other models were produced at 32/year starting mid 2021, then there would at most be 30-35 in existence right now. TSMCs goal was to get 60 systems shipped by 2023.
I would bet there is a 40/40/20 split between TSMC / Intel / Samsung on the new models. That would be like 12/12/8 3nm capable machines each.
This means you've got way too many credited to TSMC for the N3 node.
This should not be surprising given we know TSMC delayed Apple in getting 3nm last year and this year only the top iPhone models will have the 3nm A16, the rest will continue to use the 5nm A15.
The $340M EUV systems Intel recently ordered (Jan) were the 5200 model, which doesn't exist as a shipping system yet. That is for 2024/2025.
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Intel Orders 15 EUV Lithography Systems | Electronics360
Intel has placed an order for the next-gen High-NA EUV tools to fabricate 1.8nm chips
Intel is the first chip maker that has placed an order for ASML's High-NA Twinscan EXE:5200 scanner that will allow the company to start using its 18A (1.8nm) fabrication tech starting 2025.
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Last edited:
uzzi38
Platinum Member
- Oct 16, 2019
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Nonsense IMO. If anything, it's more likely they're trying to weasel their way out of using N3 for the iGPU if you ask me.
Cough cough splutter 128EUs? cough dying cough
shady28
Platinum Member
- Apr 11, 2004
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A16 is supposed to be N3 node. However, it is only going to be on the Pro and Max models reportedly. Naturally nothing is confirmed until official release.
This makes perfect sense when you add all the numbers together. Even the M2 is not on N3 yet.
Obviously TSMC has some decent capacity if they are able to supply even the Pro / Max iPhones, and they claimed earlier this year they were doing volume N3. 'Volume' is not a very descriptive word though and is very relative. iPhone Max/Pro are certainly many millions of chips.
It will clearly be well into 2023 before we see much of anything on N3.
Something to keep in mind as well, when TSMC went to 7nm EUV, they didn't have to compete much for ASMLs capacity. Intel bought some EUV systems early on then decided to stick with DUV.
Now, TSMC has to compete for those machines with Intel (and to a lesser degree, Samsung). It's not going to be quite the same as it was back in 2017/2018 when Intel decided to do something stupid.
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N3 was never the plan for MTL, but I look forward to the rumor mongers attempting to claim otherwise when it launches. To cover their failed predictions, if nothing else.
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