Discussion Intel current and future Lakes & Rapids thread

[jpiniero]

At this rate, Apple should release a Sapphire Rapids based x86 Mac Pro towards the end of this year. Releasing the ARM Mac Pro that runs circles around SPR-W would be awesome; beating 38 core based Icelake-W should be quite easy. Also they probably want to just do one final update, so SPR-W makes more sense, since it will have a longer shelf life.

At this rate it might be a year or more before SPR-W actually becomes available if Intel can't get Icelake-W out there.

 

[IntelUser2000]

I'm not trying to be a jerk here, but I am fairly certain there weren't 8 different Haswell client CPU die layouts.

Hot Chips. They said it can have even more configurations if blocks are disabled.

 

[nicalandia]

Is there any plans in patching this at the hardware level in future lakes?


"The new exploit impacts all Intel processors released in the last several years and specific Arm core processors. Intel processors affected include the most recent 12th Gen Core Alder Lake CPUs. Surprisingly, AMD chips have shown no effect from the vulnerability at this time. "

Spectre V2 vulnerability strikes again in Intel Alder Lake & Arm CPUs, AMD chips unharmed

Intel Alder Lake and Arm CPUs attacked by the reoccurrence of Spectre V2 in a brand new branch history interface attack yesterday.

wccftech.com

 

[DrMrLordX]

Here comes Patch Tuesday. Let's see the performance hit from this exploit . . .

 

[mikk]

We did change the timing of Granite Rapids, and we had a big internal debate show on should we even keep the Granite Rapids name because it was the same platform, but it was a new core on a new process. So to some degree, it was a very different product. But some said, hey, you delayed Granite Rapids. Hey, I say I enhance Granite Rapids, with a much higher performance product, a much -- 18% process, a major new core, that's 10-plus percent in the core. So a much better product and aligned to the customers' timing.

Intel Corporation (INTC) CEO Patrick Gelsinger Presents at Morgan Stanley Technology, Media and Telecom Conference 2022 (Transcript)

Intel Corporation (NASDAQ:NASDAQ:INTC) Morgan Stanley Technology, Media and Telecom Conference 2022 March 7, 2022 2:30 PM ETCompany ParticipantsPatrick Gelsinger - CEO &...

seekingalpha.com

Interesting to hear from such revised plans. For Arrow Lake we also know that Intel delayed it from H2 2023 into 2024, at the same time they switched from TSMC 3nm to Intel 20A (CPU tile probably) and upped the GT3 graphics from 320EUs to 384EUs.

 

[Exist50]

Intel Corporation (INTC) CEO Patrick Gelsinger Presents at Morgan Stanley Technology, Media and Telecom Conference 2022 (Transcript)

Intel Corporation (NASDAQ:NASDAQ:INTC) Morgan Stanley Technology, Media and Telecom Conference 2022 March 7, 2022 2:30 PM ETCompany ParticipantsPatrick Gelsinger - CEO &...

seekingalpha.com

Interesting to hear from such revised plans. For Arrow Lake we also know that Intel delayed it from H2 2023 into 2024, at the same time they switched from TSMC 3nm to Intel 20A (CPU tile probably) and upped the GT3 graphics from 320EUs to 384EUs.

They can spin it as they like, but customers care about reliable schedules first and foremost. If they can fit in some tech upgrades without worsening the delay even more, then great, but that's historically been a dangerous strategy. Maybe worth an extra quarter or two anyways, but still worse than meeting original plans. And it's not encouraging to hear Lion Cove go from 10-12% to 10%+.

Looks like this is pushing out any chance for Intel to regain the performance crown till 2026.

 

[mikk]

He has a point, you cannot deny that. It would have been much worse if it's delayed without any upgrade from the initial cores and process node. Intel 3 years ago couldn't have done this, they would have delayed it and stuck to the initial cores. Basically they cancelled Granite Rapids and replaced it with a next generation on the same name. And you can hardly figure out the performance gains from a core which is coming in 2+ years from this message, seriously. Don't read too much into it.

 

[Exist50]

And you can hardly figure out the performance gains from a core which is coming in 2+ years from this message, seriously

Why not? The number is right from the CEO.

 

[Markfw]

Why not? The number is right from the CEO.

And you believe the CEO, after years of Intel stretching the truth and sometimes actually lying ? Not me.

 

[Exist50]

And you believe the CEO, after years of Intel stretching the truth and sometimes actually lying ? Not me.

Mate, I'm expressing disappointment and pessimism, if anything. Worst case, it's 10% IPC. Best case, it's 10-12% iso-power performance, which still wouldn't be great after so much time.

 

[ashFTW]

My guess for cores in Emerald Ripids Xeon is that it will have one more row of cores (i.e. additional 4 cores) per chiplet. So potentially up to 76 cores, some of which will have to disabled for yield purposes. Top part could be 72 cores.

 

[mikk]

Why not? The number is right from the CEO.

No running CPU silicon yet (if we go by the pre delayed roadmap), how do they exactly know this? You are reading too much into this statement. 10-plus percent can mean anything, this is such a rough estimation 2+ years before a launch it's not even worth debating at this point.

 

[uzzi38]

No running CPU silicon yet (if we go by the pre delayed roadmap), how do they exactly know this? You are reading too much into this statement. 10-plus percent can mean anything, this is such a rough estimation 2+ years before a launch it's not even worth debating at this point.

He said 10-12% at investor day btw.

2hrs 31 minutes in, iirc.

 

[nicalandia]

Quite the performance hit.


"Branch History Injection (BHI), a new flavor of the Spectre-v2 vulnerability that affects both new and old Intel processors and specific Arm models, recently came to light. Linux publication Phoronix conducted testing that shows the new BHI mitigations could produce severe performance penalties up to 35%. "

https://www.tomshardware.com/news/intel-cpus-performance-hit-spectre-v2-migitations

 

[Hitman928]

Quite the performance hit.


"Branch History Injection (BHI), a new flavor of the Spectre-v2 vulnerability that affects both new and old Intel processors and specific Arm models, recently came to light. Linux publication Phoronix conducted testing that shows the new BHI mitigations could produce severe performance penalties up to 35%. "

https://www.tomshardware.com/news/intel-cpus-performance-hit-spectre-v2-migitations

For some of the previous mitigations, Intel was able to come up with different mitigations over time that had less of a performance penalty. We'll see if that happens again or not. I wonder if the ARM cores show similar performance penalty as well. Probably won't ever see those tested for this though.

 

[nicalandia]

For some of the previous mitigations, Intel was able to come up with different mitigations over time that had less of a performance penalty. We'll see if that happens again or not. I wonder if the ARM cores show similar performance penalty as well. Probably won't ever see those tested for this though.

For now, the Mitigations are done by Linux, Michael at Phoronix will release info on performance of AMD vs Intel today or early tomorrow.

 

[Hitman928]

For now, the Mitigations are done by Linux, Michael at Phoronix will release info on performance of AMD vs Intel today or early tomorrow.

They are done on Linux by Michael by the only known method of mitigation currently known by the public.

Why would AMD need to be tested as they are reportedly unaffected by the vulnerability?

 

[nicalandia]

They are done on Linux by Michael by the only known method of mitigation currently known by the public.

Why would AMD need to be tested as they are reportedly unaffected by the vulnerability?

"These changes were all merged this afternoon into Linux 5.17 Git mainline. The patches should also be backported to the various supported stable Linux kernel series and distribution kernels in short order"

Linux Lands Mitigations For Spectre-BHB / BHI On Intel & Arm, Plus An AMD Change Too - Phoronix

www.phoronix.com

Also for AMD: "AMD for their part isn't believed to be affected by BHI and has still been making use of Retpolines on newer Zen processors. They did discover though their LFENCE/JMP-focused AMD Retpolines implementation to be racy and thus are now moving to use generic Retpolines instead. I'll have benchmarks in a separate article looking at that performance difference of AMD Retpolines compared to the generic implementation|"

 

[Hitman928]

"These changes were all merged this afternoon into Linux 5.17 Git mainline. The patches should also be backported to the various supported stable Linux kernel series and distribution kernels in short order"

Linux Lands Mitigations For Spectre-BHB / BHI On Intel & Arm, Plus An AMD Change Too - Phoronix

www.phoronix.com

Also for AMD: "AMD for their part isn't believed to be affected by BHI and has still been making use of Retpolines on newer Zen processors. They did discover though their LFENCE/JMP-focused AMD Retpolines implementation to be racy and thus are now moving to use generic Retpolines instead. I'll have benchmarks in a separate article looking at that performance difference of AMD Retpolines compared to the generic implementation|"

Yes, but again, this change is not made for BHI but for prior known vulnerabilities. It will be good to see how the mitigation strategy changes for AMD on this, but I was more curious what the effect of BHI mitigations have on ARM processors since those are vulnerable to BHI as well.

 

[nicalandia]

Yes, but again, this change is not made for BHI but for prior known vulnerabilities. It will be good to see how the mitigation strategy changes for AMD on this, but I was more curious what the effect of BHI mitigations have on ARM processors since those are vulnerable to BHI as well.

I am searching for performance number on generic retpoline on Linux and Windows



I was able to find Benchmarks on Retpoline Generic, Aside from OG ThreadRipper(1950X) they seem to do just fine. I suspect that the new tests done by Phoronix will show the same.

AMD Retpoline Benchmarks From FX To Threadripper & EPYC - Phoronix

www.phoronix.com

 

[repoman27]

Hot Chips. They said it can have even more configurations if blocks are disabled.

I looked over the Haswell coverage from HotChips 25 and ISSCC 2014, and I see that Intel did show off at least 8 different designs at that time, but they only followed through with manufacturing and selling 4 of them:

4+3, H/R, Model 70 Stepping 1, C0, 260 mm², 1.7B transistors
4+2, M/H/S, Model 60 Stepping 3, C0, 177 mm², 1.4B transistors
2+3 ULT, U/Y, Model 69 Stepping 1, C0, 181 mm², 1.3B transistors
2+2 ULT, U/Y, Model 69 Stepping 1, D0, 131 mm², 0.96B transistors

I was wrong in thinking the two ULT steppings were the same layout. The die sizes and transistor counts are from Intel.

 

[jpiniero]

He has a point, you cannot deny that. It would have been much worse if it's delayed without any upgrade from the initial cores and process node. Intel 3 years ago couldn't have done this, they would have delayed it and stuck to the initial cores.

That's basically what Emerald is.

Granite sounds like they sent it back to the drawing board with the switch to a design more like Rome/Milan and they decided to include an updated core design while they were at it. The question will be will it get another delay between now and 2024.

 

[IntelUser2000]

4+3, H/R, Model 70 Stepping 1, C0, 260 mm², 1.7B transistors
4+2, M/H/S, Model 60 Stepping 3, C0, 177 mm², 1.4B transistors
2+3 ULT, U/Y, Model 69 Stepping 1, C0, 181 mm², 1.3B transistors
2+2 ULT, U/Y, Model 69 Stepping 1, D0, 131 mm², 0.96B transistors

There must be a 2+1 as well. The Celeron and/or Pentium uses GT1 graphics.

Anyway the point was that even far as back then they had more configurations despite the potentially better yield. They also did that with Atoms having six or so separate dies.

If they were able to do that back then, why did they regress on that department with Tigerlake/Alderlake having "horrible yield" as some like to think?

No running CPU silicon yet (if we go by the pre delayed roadmap), how do they exactly know this? You are reading too much into this statement. 10-plus percent can mean anything, this is such a rough estimation 2+ years before a launch it's not even worth debating at this point.

You really think the CEO wouldn't know? They might not have concrete details for some such as clock speeds but they will have a reasonably good idea about how it'll perform. Architectures are laid out in advance and set in stone at one point.

@ashFTW Right now the top SPR configuration has 16 cores per die. Rumors are EMR will end up with 64 cores. 72 cores are only possible if the rumored 72 core die exist and can be manufactured by that time. Guess it'll be better but it's like if Rocketlake ended up using 10% less power.

 

[ashFTW]

Right now the top SPR configuration has 16 cores per die. Rumors are EMR will end up with 64 cores. 72 cores are only possible if the rumored 72 core die exist and can be manufactured by that time. Guess it'll be better but it's like if Rocketlake ended up using 10% less power.

The image below is from TechPowerUp, showing 15 cores per SPR chiplet. For yield reasons one core per chiplet is being fused off, giving 56 cores for the SPR chip with 4 chiplets. I’m assuming this is the largest SPR (XCC) chiplet. Intel has said that the EMR will have more cores, and I know the rumor is 64 cores. But the only way to add more cores to this die with total 64 or above is to add another row/column of 4 additional cores, which make the max cores for EMR to be 19x4=76 cores. If one core per chiplet is fused off, we get 72 cores. Only if 3 cores per chiplet need fusing off, do we get 64 cores, which I think is quite unlikely. Intel 7 yields should improve over SPR with one year to go. Maybe Intel is being defensive and quoting 64, but the number will go up closer to the launch date.

 

[Exist50]

But the only way to add more cores to this die with total 64 or above is to add another row/column of 4 additional cores

Emphasis mine.