Discussion Intel current and future Lakes & Rapids thread

[Henry swagger]

https://twitter.com/x/status/1495052786542784521

meteor lake floor plan.. looks amazing

 

[Exist50]

https://twitter.com/x/status/1495052786542784521

meteor lake floor plan.. looks amazing

That's not even remotely accurate... Hell, that's not even MTL-P!

 

[Saylick]

Does Meteorlake use EMIB or some kind of vertical stacking? If EMIB, some of those dies are pretty skinny in one dimension, and seeing how much space EMIB takes up on Sapphire Rapids, it doesn't seem area efficient if a given tile is like half EMIB.

 

[coercitiv]

Ok, that's a good point. @coercitiv chip is running at under 45C, when laptops typically run at 70C+.

The mobile 500 series chipset only had a 2.9W TDP.

It's weekend, so more time for the low TDP tests

First of all, according to Jarrod, the MSI laptop has quite a nice cooling solution (/w liquid metal applied) that stays within 64C @ 45W TDP and ambient temps of about 21C:



So I stopped most of my fans, covered the top of the case with travel books, and ran CB23 a few times to warm the air inside the case until the CPU started "cruising" around 65C while running the bench. In order to make this an apples to apples comparison and also to make thermal tuning easier, I decided to simulate 45W TDP. That meant a 42W power limit as we subtract 3W for the missing PCH. This time the test was done with HWInfo running: monitoring data was reset just after hitting the Start button, stopped the second I saw the score. As you can see the CPU started "hot" at 62C and had an average temp of 66C during the bench.

The 6+4 config scored 12400 in CB23. By comparison the mobile 6+8 config scored 11800 @ 45W.



Something is still amiss. We can keep looking for differences that break the comparison, like the 3600 DDR4 on my machine and 4800 DDR5 on the laptop (with much worse timings), but I doubt that's an actual advantage in this bench. It boggles the mind to see higher or equal scores from desktop 6+4 against mobile 6+8 using lower TDP points such as 45W or 25W. The 12900HK should be a premium binned part, it should have no issue against a perfectly average 12700K.

Maybe this can be explained by some other mobile platform quirk, it would be very disappointing if ADL-P binning variance is that high.

 

[DrMrLordX]

That is certainly what they appear to be saying, since Intel 4 is their first EUV process.

Ugh. Don't believe that even for a second.

No, it's not. They're not delaying it for quarter after quarter because of process yields.

You gotta wonder though, something might be wrong with yields of 10ESF as you get closer to the reticle limit. We already know yields on 10nm+ were awful when fabbing IceLake-SP. Or at least we reasonably expect that, since it was horribly delayed; took forever to reach market in volume; and may have been a significant factor in Intel experiencing lower margins for 10nm products (as seen in their most recent earnings reports). On 10ESF, Intel has curiously chosen not to experiment with Alder Lake or Raptor Lake in any way that permits them to produce CPUs with more Golden Cove/Raptor Cove cores. They've avoided larger monolithic dice, and they've avoided tiles (tiles won't arrive until Meteor Lake, or so we're told).

Sapphire Rapids has tiles that are, what, 400mm2 in size? That is larger than a monolithic Alder Lake-S (~212mm2). There is a definite possibility that Intel is experiencing yield problems on those Sapphire Rapids tiles!

 

[coercitiv]

Don't believe that even for a second.

That's less than 0.05 wafers for anyone looking for a wph conversion.

 

[eek2121]

Given that Icelake Server's launch was basically last quarter, it sure looks that way.

Looks like EMIB takes up around 21% of the chip. That's really a lot. Back with Epyc Naples AMD talked about an MCM area overhead of ~10%. For SPR Intel is essentially more than doubling that overhead to offer monolithic-like latency.

Yes, and keep in mind how big and power hungry Golden Cove is. Now stack 60 of them on a chip. 😂

Ugh. Don't believe that even for a second.

Are you saying that Intel and ASML are colluding to lie to investors?

 

[DrMrLordX]

Are you saying that Intel and ASML are colluding to lie to investors?

Intel didn't even have that kind of wafer volume on 14nm in its peak; furthermore, Intel is still short EUV equipment, unless ASML magicked up a few extra machines that industry analysts just didn't notice.

 

[eek2121]

Intel didn't even have that kind of wafer volume on 14nm in its peak; furthermore, Intel is still short EUV equipment, unless ASML magicked up a few extra machines that industry analysts just didn't notice.

@DrMrLordX FYI this is the machine Intel is currently using: TWINSCAN NXE:3600D - EUV lithography systems | ASML

1 machine produces >= 160 wph according to ASML.

 

[Henry swagger]

Ugh. Don't believe that even for a second.



You gotta wonder though, something might be wrong with yields of 10ESF as you get closer to the reticle limit. We already know yields on 10nm+ were awful when fabbing IceLake-SP. Or at least we reasonably expect that, since it was horribly delayed; took forever to reach market in volume; and may have been a significant factor in Intel experiencing lower margins for 10nm products (as seen in their most recent earnings reports). On 10ESF, Intel has curiously chosen not to experiment with Alder Lake or Raptor Lake in any way that permits them to produce CPUs with more Golden Cove/Raptor Cove cores. They've avoided larger monolithic dice, and they've avoided tiles (tiles won't arrive until Meteor Lake, or so we're told).

Sapphire Rapids has tiles that are, what, 400mm2 in size? That is larger than a monolithic Alder Lake-S (~212mm2). There is a definite possibility that Intel is experiencing yield problems on those Sapphire Rapids tiles!

Tiger lake shipped 50 million units how are yields terrible ?

 

[Markfw]

Tiger lake shipped 50 million units how are yields terrible ?

Yields on a small die are a lot better than yields on a very large die.

 

[Exist50]

If yields were the problem, then Intel would just launch, but with lower volume. Intel's biggest issue right now is incompetence on the design side. It's why we get absurdities like Intel saying Intel 4 will be ready by end of '22 but we won't get products till H2'23.

 

[JasonLD]

If yields were the problem, then Intel would just launch, but with lower volume. Intel's biggest issue right now is incompetence on the design side. It's why we get absurdities like Intel saying Intel 4 will be ready by end of '22 but we won't get products till H2'23.

6 months is typical time window from the process being ready to mass production to actual launch.

 

[Exist50]

6 months is typical time window from the process being ready to mass production to actual launch.

Let's be clear, MTL will probably only start mass production in Q3, maybe way end of Q2. There's going to be like half a year where, if Intel is to be believed, the process is ready for mass production but no architecture is.

 

[Accord99]

Maybe this can be explained by some other mobile platform quirk, it would be very disappointing if ADL-P binning variance is that high.

What's the core voltage when it's running R23? If it's 1.155v that seems very high for a P-core clock of only 3.2 GHz. On a 11800H laptop that I have, the voltage at 3.2GHz all-core is only 0.9v at default settings.

 

[jpiniero]

If yields were the problem, then Intel would just launch, but with lower volume.

I'm sure that's the plan. If Icelake Server is any indication you won't really be able to buy it until Q4 anyway.

 

[IntelUser2000]

Let's be clear, MTL will probably only start mass production in Q3, maybe way end of Q2. There's going to be like half a year where, if Intel is to be believed, the process is ready for mass production but no architecture is.

So the whole thing about Jim Keller going in and fixing the way designs and validations are done because either they were archaic and/or horribly inefficient still exists.

Even with the process delays it still sounds like the weakness is the design. Pretty wacky.

On 10ESF, Intel has curiously chosen not to experiment with Alder Lake or Raptor Lake in any way that permits them to produce CPUs with more Golden Cove/Raptor Cove cores. They've avoided larger monolithic dice, and they've avoided tiles (tiles won't arrive until Meteor Lake, or so we're told).

The process is more expensive than previous generations you know? That's an industry trend.

They don't have tiles since they are not ready yet.

 

[jpiniero]

Does Meteorlake use EMIB or some kind of vertical stacking? If EMIB, some of those dies are pretty skinny in one dimension, and seeing how much space EMIB takes up on Sapphire Rapids, it doesn't seem area efficient if a given tile is like half EMIB.

It does appear that it is using Foveros. Not active though so I'm not sure why they are using 10 nm for it.

 

[IntelUser2000]

Maybe this can be explained by some other mobile platform quirk, it would be very disappointing if ADL-P binning variance is that high.

Seems like a possibility though isn't it? HWB is getting 13K for the same point.

Let's be clear, MTL will probably only start mass production in Q3, maybe way end of Q2. There's going to be like half a year where, if Intel is to be believed, the process is ready for mass production but no architecture is.

MLID is saying Q4 for RPL H/HX/U. So still leaves the possibility for a low volume chip like the 5W M parts in Q2. Reminds me of the 14nm delay and the Core M release. Boy that was disappointing, after all the claims of performance and power management improvements. I hope it's much better this time.

The twitter speculation is completely off as said by @Exist50

It does appear that it is using Foveros. Not active though so I'm not sure why they are using 10 nm for it.

I am not keeping close track, but the 10nm process might have a Foveros variant that's useful for Meteorlake. Point of a passive die is to just connect them together.

 

[IntelUser2000]

Looks like they changed the Meteorlake graphics architecture from DG2 based to Battlemage DG3 based. Good thing because the architecture in DG2 isn't particularly competitive.

Some say Raja will have a hard time since he was handed the "worst" GPU architecture in the industry.

 

[Exist50]

So the whole thing about Jim Keller going in and fixing the way designs and validations are done because either they were archaic and/or horribly inefficient still exists.

While I wouldn't say Intel's design practices are 100% up to date, I think for MTL in particular, it can be primarily blamed on idiotic, last minute, top-down design decisions with no regard for a realistic schedule.

It does appear that it is using Foveros. Not active though so I'm not sure why they are using 10 nm for it.

Where did you see that the base die is using 10nm?

Looks like they changed the Meteorlake graphics architecture from DG2 based to Battlemage DG3 based. Good thing because the architecture in DG2 isn't particularly competitive.

I'm not necessarily convinced. The only thing that even hints at such a change is both Meteor Lake and Battlemage showing up in the same column on a diagram with time/generation as the axis. I'd still bet that it uses DG2 IP.

 

[IntelUser2000]

So from Intel's perspective, they wanted Icelake to be early Q1 of last year. But that didn't work out. Some must have wanted Sapphire Rapids to be Q4 of last year but that's unrealistic because it's a sweeping platform change and vendors will protest against it.

And Sapphire Rapids is having problems and that puts us to Q2/Q3 of this year. We would have thought and hoped Granite Rapids to be Q2 of next year but I bet you the problems with Sapphire Rapids mean some fleshing out is required, so Emerald Rapids.

Sapphire Rapids delay isn't the big deal, but the existence of Emerald Rapids is, because it effectively pushes out the roadmap out by 1 year. Sounds like to be they are having problems with the first tile implementation. In paper they can shorten the lifespan of Emerald Rapids but not sure how realistic that is. Never happened before.

If the condition was so bad that threat of Emerald Rapids was always looming then technically Granite Rapids on Intel 3 is a pull-in rather than a delay. But to us it makes no difference.

The original Granite Rapids was 120 cores? Stands to reason we'll see something like 160 cores on the Intel 3 version. It might actually end up being competitive if they can pull it off with something like 4x the performance of Sapphire Rapids.

I'm not necessarily convinced. The only thing that even hints at such a change is both Meteor Lake and Battlemage showing up in the same column on a diagram with time/generation as the axis. I'd still bet that it uses DG2 IP.

They are calling it with new terminologies such as "tGPU" And it says it's tiled GPU which they don't seem to have it down with DG2 but will get there with Battlemage.

 

[Exist50]

Sapphire Rapids delay isn't the big deal, but the existence of Emerald Rapids is, because it effectively pushes out the roadmap out by 1 year. Sounds like to be they are having problems with the first tile implementation

I'm not sure if tiles are to blame. Ice Lake SP was a train wreck despite being monolithic.

The original Granite Rapids was 120 cores? Stands to reason we'll see something like 160 cores on the Intel 3 version.

I could maybe believe the number, but not the reason. Intel 3 isn't a shrink; it's just a refinement/extension. So they're not getting anything from process, and they have a new core to fit in. Honestly, I think Turin will still have the edge.

They are calling it with new terminologies such as "tGPU" And it says it's tiled GPU which they don't seem to have it down with DG2 but will get there with Battlemage.

I think the "tile" nomenclature is orthogonal from the graphics IP. Maybe they'll use Battlemage for Arrow Lake though?

 

[jpiniero]

Where did you see that the base die is using 10nm?

I forget where I saw that.

Sapphire Rapids delay isn't the big deal, but the existence of Emerald Rapids is, because it effectively pushes out the roadmap out by 1 year. Sounds like to be they are having problems with the first tile implementation. In paper they can shorten the lifespan of Emerald Rapids but not sure how realistic that is. Never happened before.

I'm assuming it's not a tile implementation issue, it's a 7 nm issue.

I'm not sure if tiles are to blame. Ice Lake SP was a train wreck despite being monolithic.

Well that's because of the yields. It's actually quite amazing they are still selling tons of 14 nm Xeons.

 

[Exist50]

Well that's because of the yields. It's actually quite amazing they are still selling tons of 14 nm Xeons.

Again, I think blaming yields for everything is just wrong. What stepping is Ice Lake SP on again? E-step or thereabouts?