LightningZ71
Golden Member
- Mar 10, 2017
- 1,628
- 1,898
- 136
I think that it would be technically interesting for them to release a 32 core gracemont product on the same die footprint as the 6+8 die.
I would have to see a 12900k's performance when power limited to 45W or 65W before I would agree with that statement.
0+8 is a pretty weird config for an M SKU though. You'd think that if Gracemont matches expectations, 4 would be plenty for low end devices. 0+8 will have some interesting overlap with a theoretical 1+4 or similar.
0+8 is a pretty weird config for an M SKU though. You'd think that if Gracemont matches expectations, 4 would be plenty for low end devices. 0+8 will have some interesting overlap with a theoretical 1+4 or similar.
What I meant with this was that if it was a proper desktop chip meant to compete against the 5950X for example, it would have had a larger config - 6+16 or 8+16 or heck 10+16!
Even if it was 50% faster than Tremont, which is a tremendous achievement it won't end up being anywhere near 10700K in MT.
The 10700K gets 5000 points in R20 MT while the Tremont N6005 gets 925. Maybe it'll do little better than 50% and the 4 core Gracemont gets 1400. You multiply that by 1.9x for double the cores and you end up with 2650. Realistically it'll probably need to be rated at 18W to get that or need to reduce clocks and you'll get 2300 points or so, which is less than half of the 10700K.
That puts it pretty close to the T variant of Cometlake chips. But the difference is that the N chips typically are rock solid when it comes to maintaining frequency at that power levels. So what you get under 30 second loading is pretty much what you get under 3 hour loading.
The 3k+ obtained in 12900K will not translate in mobile, @IntelUser2000 estimate was based on lower power figures than what ADL-S is likely pumping through E cores to maximize throughput. I wouldn't be surprised if a 4-core complex is using 20W+ for those high CB20 scores, meaning 40W for 8 cores. Scaling back to 10W per core complex will come with a relatively small performance penalty, but a penalty nonetheless.The N6005 has 1.5MB shared L2 cache between the 4 cores while Gracemont has 4 MB shared L2 Cache per 4 core complex, so Gracemont should probably scale significantly better in MT workloads than Tremont. Since we know a 12900k gets 10.5-11k in R20MT & a 12400 gets less than 5k in R20MT, the math doesn't work out unless the Gracemont complex accounts for quite a bit above 3k or so. Nowhere near a 10700k (way lower clocks and no HT all but guarantee this), but would be more than respectable for any mobile application even without Golden Cove.
N has historically been its own die. Should be the same for whatever this is.
You have to remember, these chips don't have hyperthreading.0+8 is a pretty weird config for an M SKU though. You'd think that if Gracemont matches expectations, 4 would be plenty for low end devices. 0+8 will have some interesting overlap with a theoretical 1+4 or similar.
That's true but it's going to be awhile before OEMs quit 14 nm Atoms.
Who in retail is still using Goldmont Plus? I can't even find any sold in AiOs or desktops in the United States like the old days. They've all switched to newer Pentium Golds; for example, the cheapest AiOs from Dell use the Pentium Gold 7505 which is a 2c/4t TigerLake. It's very much a mobile product in a desktop form factor (which is typical for cheap AiOs), but it isn't Goldmont Plus.
Even if it was 50% faster than Tremont, which is a tremendous achievement it won't end up being anywhere near 10700K in MT.
The 10700K gets 5000 points in R20 MT while the Tremont N6005 gets 925. Maybe it'll do little better than 50% and the 4 core Gracemont gets 1400. You multiply that by 1.9x for double the cores and you end up with 2650. Realistically it'll probably need to be rated at 18W to get that or need to reduce clocks and you'll get 2300 points or so, which is less than half of the 10700K.
That puts it pretty close to the T variant of Cometlake chips. But the difference is that the N chips typically are rock solid when it comes to maintaining frequency at that power levels. So what you get under 30 second loading is pretty much what you get under 3 hour loading.
Don't forget N6005 does not support AVX2.
No guaranties that these new SKUs will support it either, Intel would not want to sell cheapo 8C with potent FP performance and power efficiency.
I hope not, losing enough P cores on 6+8 dice to create a separate 0+8 SKU would be bad news from a process perspective.Could even be the 6+8 die although it would have to use the P packing instead.
I hope not, losing enough P cores on 6+8 dice to create a separate 0+8 SKU would be bad news from a process perspective.
It also seems highly unlikely from a statistical point-of-view to have defects in all 6 P cores and no defects in any of the 8 e cores.
I believe Ian write there will be 3 dies, 8+8 desktop, 6+4 mobile, and 2+8 ultramobile.
The 2+8 configuration looks to be a great part if we are looking at Gracemont being super-efficient, equal-to-Skylake performing cores.
It also seems highly unlikely from a statistical point-of-view to have defects in all 6 P cores and no defects in any of the 8 e cores.
Laptops mainly.
But the 0+8 would also be a extremely low volume product too. There's other considerations like stable clock speed or the IGP (Intel hasn't IIRC sold an U product without the IGP enabled... officially anyway)
Wait, why would 0+8 be low volume? Yields on such a tiny chip should be pretty high, and the Asian market would eat it up like mad.
I would think that if there is a fifth die, it would be 0+4+1. The 0+8 would only be busted P core dies with good E dies, which yes would be statistically rare.
No, four known dies:
8+8+1 desktop
6+0+1 desktop
6+8+2 mobile
2+8+2 mobile
And now possibly a fifth 0+8+? N die.
Where did you read about the 6+1 die? I didn't know about this.
The chance that Intel will use P/S dies for N are slim to none.
-Astronomically low chance that only Golden Cove portion will fail and nowhere else. Not the Gracemont portion, not the caches, and not the uncore.
-Disabled die means you still end up with the larger physical die. In case of the N chips, the sheer physical size of the P/S dies will limit how small packaging can be.
-They'd have to go intentionally disable some of the GPU part so it doesn't cannibalize the rest. Also the PCI Express and the uncore. Why, when you can just make a separate N die?