The chance that Intel will use P/S dies for N are slim to none.
-Astronomically low chance that only Golden Cove portion will fail and nowhere else. Not the Gracemont portion, not the caches, and not the uncore.
-Disabled die means you still end up with the larger physical die. In case of the N chips, the sheer physical size of the P/S dies will limit how small packaging can be.
-They'd have to go intentionally disable some of the GPU part so it doesn't cannibalize the rest. Also the PCI Express and the uncore. Why, when you can just make a separate N die?
-Intel knows how to make multiple dies even though the volume is pretty much in the hobbyist grade range. They made 6 or so different dies for Atom in the 45nm generation. I doubt some dies sold above 10K units.
Disabling dies to make totally new lineup is a 1998 thing. Hello! It's 2021!
@diediealldie I believe Gracemont will gain some from enabling AVX. But that amount will be small. From what I can gather, there's zero from AVX2. AVX gains might be 5%, maybe at best 10%. Even then, any gain from "floating point units" may be due to the fact that they enhanced the dataflow on the FP side, not so much as the 256-bit width and registers AVX offers.
Also, I don't believe caches benefitted Cinebench to any measurable degree. If Gracemont 10W does better than my estimations it'll be purely due to the fact that it's a better architecture than I expected.
That should be a pleasant surprise for the pro-x86 guys as well. Gracemont may end up being a great demonstration that implementation and creativity of the human mind can more than make up for a possibly deficient ISA. Also, ARM isn't just about the ISA but it has a massive industry support behind it. You put more people to work, you have a better chance of making it turn out better. Simple as that.