Ajay
Lifer
- Jan 8, 2001
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Not enough info yet to decide on that yet? Need to see more reasonable clocks for P-cores and not ballistic 5Ghz+ all core. Huge part of AMD efficiency came from being able too run MT at joke clock levels and voltages and still beat the hell out of Intel's 14nm stuff.For about 10% IPC increase versus Zen3, Golden Cove looks to be very inefficient power wise. I don't know if it's the issue with the process node or uarch. itself, but perf./watt is noticeably worse.
Oh I agree that we should wait for final benchmarks, I'm just saying that it doesn't look good right now. Hopefully it will be better on launch with polished BIOS versions.Not enough info yet to decide on that yet? Need to see more reasonable clocks for P-cores and not ballistic 5Ghz+ all core. Huge part of AMD efficiency came from being able too run MT at joke clock levels and voltages and still beat the hell out of Intel's 14nm stuff.
Apparently they also confirmed that Meteor Lake uses a foundry node for some portion of it. I wonder if this does mean that the CPU tile is being dual sourced.Looks like the CPU tile portion of Meteor Lake has now powered on (Intel 4 process):
Given that all the leaks have basically been ridiculous overclocks thus far, I think it's far too early to make even that decision. Has anyone gotten Zen 3 up to 5.2 GHz all core?Oh I agree that we should wait for final benchmarks, I'm just saying that it doesn't look good right now. Hopefully it will be better on launch with polished BIOS versions.
Do we know the power consumption of the 5800X all cores @4.9GHz running the same bench?It looks like architecture and/or 10nm++ process is still behind the competitors.
I wonder if that's the 192EU integrated graphics in Meteor Lake? Would make sense now that Arc has been announced on TSMC N6 that perhaps Intel would use TSMC for the graphics as long as they're there.Apparently they also confirmed that Meteor Lake uses a foundry node for some portion of it. I wonder if this does mean that the CPU tile is being dual sourced.
And who says just graphics? Wonder what that SoC chiplet is on...I wonder if that's the 192EU integrated graphics in Meteor Lake? Would make sense now that Arc has been announced on TSMC N6 that perhaps Intel would use TSMC for the graphics as long as they're there.
Disregarding the uncore and the E core contribution to power, 233W to 330W is more than the voltage squared and frequency increase.Voltage too high, Golden Cove scaling is off. At 4.0 Ghz (i5-12400) Golden Cove is probably a very efficient core but not at around 5 Ghz.
I wouldn't focus too much on the pipeline depth. Wider and deeper is an ongoing trend that doesn't necessarily imply super high clock speeds. That said, those high clocks are problematic, and Golden Cove doesn't deviate significantly from its predecessors. And unfortunately there seems to be no end in sight. I'd bet good money that by the end of 2025 there'll be a desktop chip that can hold a 6GHz overclock stable on AIO cooling.Disregarding the uncore and the E core contribution to power, 233W to 330W is more than the voltage squared and frequency increase.
If you assume Golden Cove is only responsible for 180W out of that 233W, then you are talking 180W to 277W which is 24% above what V2F law would give you.
I'm telling you guys, 5-plus GHz frequencies are meant for the insane asylum. That's why it has been reserved for water cooling+ setups for decades, until very recently when the air HSF setups became these bricks with massive server-like fans strapped on them.
Intel added an extra pipeline stage to Golden Cove because they still haven't gave up on their Netburst dream of 20 years ago. That extra pipeline stage would have gave them 2-4% extra performance per clock so Golden Cove might have been 21-23% faster per clock, not 19%. The extra pipeline stage also increases complexity and thus transistors and thus power use. This explains the less than expected perf/clock gain.
If you need nothing but the fastest performance, this may be the way to go, but at a sacrifice of everything else. The inefficient Golden Cove means you end up with inefficient Sapphire Rapids and inefficient mobile chips.
Given that all the leaks have basically been ridiculous overclocks thus far, I think it's far too early to make even that decision. Has anyone gotten Zen 3 up to 5.2 GHz all core?
Oh I see we both were seeking the same thing.Do we know the power consumption of the 5800X all cores @4.9GHz running the same bench?
It's cute that anyone is even looking at the power consumption for all-core 5+ GHz overclocks. I bash on Intel for power usage issues all the time, but if you are going to compare Intel, let's compare performance based on a similar power envelope. That is, If you can't get Zen 3 to hit 5.3 GHz all core, don't look at Intel products that DO hit that point and claim they are inefficient. Take the max Zen 3 all core clocks and compare them to Intel equivalents, and see who gets more work done. Then we will have a starting point to see who is more efficient.Disregarding the uncore and the E core contribution to power, 233W to 330W is more than the voltage squared and frequency increase.
If you assume Golden Cove is only responsible for 180W out of that 233W, then you are talking 180W to 277W which is 24% above what V2F law would give you.
I'm telling you guys, 5-plus GHz frequencies are meant for the insane asylum. That's why it has been reserved for water cooling+ setups for decades, until very recently when the air HSF setups became these bricks with massive server-like fans strapped on them.
Intel added an extra pipeline stage to Golden Cove because they still haven't gave up on their Netburst dream of 20 years ago. That extra pipeline stage would have gave them 2-4% extra performance per clock so Golden Cove might have been 21-23% faster per clock, not 19%. The extra pipeline stage also increases complexity and thus transistors and thus power use. This explains the less than expected perf/clock gain.
If you need nothing but the fastest performance, this may be the way to go, but at a sacrifice of everything else. The inefficient Golden Cove means you end up with inefficient Sapphire Rapids and inefficient mobile chips.
Don’t forget that leakage current has a cubic relationship to voltage.Disregarding the uncore and the E core contribution to power, 233W to 330W is more than the voltage squared and frequency increase.
If you assume Golden Cove is only responsible for 180W out of that 233W, then you are talking 180W to 277W which is 24% above what V2F law would give you.
Are people also getting boards to go with them?Same story as with Rocket Lake, CPU-s are sold before official launch=still NDA in active.
That's a head-scratcher. How in the heck did Intel NOT put them on separate voltage domains?Smaller cores are actually quite inefficient at full CPU throughput because they are fed the full voltage required by the big cores running at 5GHz.
A separate voltage rail for the small cores is necessary for full throughput being efficient, currently small cores are overvolted by something like 20% over what would be enough to get good stability at 3.7, that s roughly 40% more power than necessary.
Probably necessary for reasons of volume. There won't be that much "Intel 4" to go around.Apparently they also confirmed that Meteor Lake uses a foundry node for some portion of it. I wonder if this does mean that the CPU tile is being dual sourced.
@Abwx explains it fairly well in post #13774.That's a head-scratcher. How in the heck did Intel NOT put them on separate voltage domains?
We already know how big Golden coves are by looking at Sapphire rapids dies. Since Intel 10 (7?) density is similar to that of TSMC7, a comparison is relatively easy.For about 10% IPC increase versus Zen3, Golden Cove looks to be very inefficient power wise. I don't know if it's the issue with the process node or uarch. itself, but perf./watt is noticeably worse. Especially if you take into consideration die size and how much intel invested in beefing up the core.
This is stock XMPThere already is DDR5 memory with both a higher frequency and noticeably lower latency than what that poster used:
6600 MT/s with CL36 is a 10.9 ns latency for the memory, who knows if the specific implementation would add more to that.
Bandwidth of DDR4 4200 and latency of mobile phone. Achievement in handicapping stock performance of your new CPU core is now unlocked.
Intel would have been better-served by going with two rails, even if it cost them a little more per chip and added a little complexity. Even those non-OC power results are a bit ugly. If they could dial it back a little then it would be good for Alder Lake-S and great for Alder Lake-P.@Abwx explains it fairly well in post #13774.
So they'd have actually had to make up a desktop oriented chip, and they didn't. It's a scaled up mobile chip.
If small cores optimal voltage result in 50W power then 20% overvoltage result in 25W more power, that s not enough delta to make a dual rail relevant given not only cost/complexity but also reliability, not counting complicated power management.Intel would have been better-served by going with two rails, even if it cost them a little more per chip and added a little complexity. Even those non-OC power results are a bit ugly. If they could dial it back a little then it would be good for Alder Lake-S and great for Alder Lake-P.
As expected, "in real world bench as Cinebench+i9 12900K(stock setings) will need 100W+ more for very similar R9 5950X score."
From 4.9-->5.2 Ghz= +100W
From 5.2-->5.3 Ghz=+70W
Voltage too high, Golden Cove scaling is off. At 4.0 Ghz (i5-12400) Golden Cove is probably a very efficient core but not at around 5 Ghz.
How would the chip become less reliable? Is Intel really that incompetent?that s not enough delta to make a dual rail relevant given not only cost/complexity but also reliability, not counting complicated power management.
That would be if voltage curves are the same. If anything i'd expect E cores to request less voltage due to simple physics of drawing less amperage and less VDroop compensation needed.And as said in mobile P cores will clock close to the E cores frequencies, hence E cores overvoltage will be only 4% if P cores work at 4GHz.