Discussion Intel current and future Lakes & Rapids thread

[Abwx]

Yeah, i was disappointed to read they share same VCC domain as big cores. Those things really need their own VID tables and separate voltage rail to really shine in OC scenarios. Mobile origins of this CPU are showing up once more.

On a DT SKU this would necessitate a 100W VR just for the small cores, that s too much added cost and complexity for the benefit, and in mobile frequency of the P cores will be low enough as to render dual rails useless, seems to me that AMD s such solution for CPU and iGPU wasnt a success and that the common supply ended being generalised in OEMs designs.

 

[inf64]

For about 10% IPC increase versus Zen3, Golden Cove looks to be very inefficient power wise. I don't know if it's the issue with the process node or uarch. itself, but perf./watt is noticeably worse. Especially if you take into consideration die size and how much intel invested in beefing up the core.

 

[Ajay]

Other known twitter guys are also posting the same

https://twitter.com/x/status/1451105188643672069

Du Du Duh!

 

[dullard]

Looks like the CPU tile portion of Meteor Lake has now powered on (Intel 4 process):

https://images.anandtech.com/doci/17026/Q364.png

 

[JoeRambo]

For about 10% IPC increase versus Zen3, Golden Cove looks to be very inefficient power wise. I don't know if it's the issue with the process node or uarch. itself, but perf./watt is noticeably worse.

Not enough info yet to decide on that yet? Need to see more reasonable clocks for P-cores and not ballistic 5Ghz+ all core. Huge part of AMD efficiency came from being able too run MT at joke clock levels and voltages and still beat the hell out of Intel's 14nm stuff.

 

[inf64]

Not enough info yet to decide on that yet? Need to see more reasonable clocks for P-cores and not ballistic 5Ghz+ all core. Huge part of AMD efficiency came from being able too run MT at joke clock levels and voltages and still beat the hell out of Intel's 14nm stuff.

Oh I agree that we should wait for final benchmarks, I'm just saying that it doesn't look good right now. Hopefully it will be better on launch with polished BIOS versions.

 

[jpiniero]

Looks like the CPU tile portion of Meteor Lake has now powered on (Intel 4 process):

https://images.anandtech.com/doci/17026/Q364.png

Apparently they also confirmed that Meteor Lake uses a foundry node for some portion of it. I wonder if this does mean that the CPU tile is being dual sourced.

 

[eek2121]

Oh I agree that we should wait for final benchmarks, I'm just saying that it doesn't look good right now. Hopefully it will be better on launch with polished BIOS versions.

Given that all the leaks have basically been ridiculous overclocks thus far, I think it's far too early to make even that decision. Has anyone gotten Zen 3 up to 5.2 GHz all core?

 

[Hulk]

It looks like architecture and/or 10nm++ process is still behind the competitors.

Do we know the power consumption of the 5800X all cores @4.9GHz running the same bench?

 

[bwhitty]

Apparently they also confirmed that Meteor Lake uses a foundry node for some portion of it. I wonder if this does mean that the CPU tile is being dual sourced.

I wonder if that's the 192EU integrated graphics in Meteor Lake? Would make sense now that Arc has been announced on TSMC N6 that perhaps Intel would use TSMC for the graphics as long as they're there.

 

[Exist50]

I wonder if that's the 192EU integrated graphics in Meteor Lake? Would make sense now that Arc has been announced on TSMC N6 that perhaps Intel would use TSMC for the graphics as long as they're there.

And who says just graphics? Wonder what that SoC chiplet is on...

 

[IntelUser2000]

Voltage too high, Golden Cove scaling is off. At 4.0 Ghz (i5-12400) Golden Cove is probably a very efficient core but not at around 5 Ghz.

Disregarding the uncore and the E core contribution to power, 233W to 330W is more than the voltage squared and frequency increase.

If you assume Golden Cove is only responsible for 180W out of that 233W, then you are talking 180W to 277W which is 24% above what V2F law would give you.

I'm telling you guys, 5-plus GHz frequencies are meant for the insane asylum. That's why it has been reserved for water cooling+ setups for decades, until very recently when the air HSF setups became these bricks with massive server-like fans strapped on them.

Intel added an extra pipeline stage to Golden Cove because they still haven't gave up on their Netburst dream of 20 years ago. That extra pipeline stage would have gave them 2-4% extra performance per clock so Golden Cove might have been 21-23% faster per clock, not 19%. The extra pipeline stage also increases complexity and thus transistors and thus power use. This explains the less than expected perf/clock gain.

If you need nothing but the fastest performance, this may be the way to go, but at a sacrifice of everything else. The inefficient Golden Cove means you end up with inefficient Sapphire Rapids and inefficient mobile chips.

 

[Exist50]

Disregarding the uncore and the E core contribution to power, 233W to 330W is more than the voltage squared and frequency increase.

If you assume Golden Cove is only responsible for 180W out of that 233W, then you are talking 180W to 277W which is 24% above what V2F law would give you.

I'm telling you guys, 5-plus GHz frequencies are meant for the insane asylum. That's why it has been reserved for water cooling+ setups for decades, until very recently when the air HSF setups became these bricks with massive server-like fans strapped on them.

Intel added an extra pipeline stage to Golden Cove because they still haven't gave up on their Netburst dream of 20 years ago. That extra pipeline stage would have gave them 2-4% extra performance per clock so Golden Cove might have been 21-23% faster per clock, not 19%. The extra pipeline stage also increases complexity and thus transistors and thus power use. This explains the less than expected perf/clock gain.

If you need nothing but the fastest performance, this may be the way to go, but at a sacrifice of everything else. The inefficient Golden Cove means you end up with inefficient Sapphire Rapids and inefficient mobile chips.

I wouldn't focus too much on the pipeline depth. Wider and deeper is an ongoing trend that doesn't necessarily imply super high clock speeds. That said, those high clocks are problematic, and Golden Cove doesn't deviate significantly from its predecessors. And unfortunately there seems to be no end in sight. I'd bet good money that by the end of 2025 there'll be a desktop chip that can hold a 6GHz overclock stable on AIO cooling.

 

[eek2121]

Given that all the leaks have basically been ridiculous overclocks thus far, I think it's far too early to make even that decision. Has anyone gotten Zen 3 up to 5.2 GHz all core?

Do we know the power consumption of the 5800X all cores @4.9GHz running the same bench?

Oh I see we both were seeking the same thing.

Disregarding the uncore and the E core contribution to power, 233W to 330W is more than the voltage squared and frequency increase.

If you assume Golden Cove is only responsible for 180W out of that 233W, then you are talking 180W to 277W which is 24% above what V2F law would give you.

I'm telling you guys, 5-plus GHz frequencies are meant for the insane asylum. That's why it has been reserved for water cooling+ setups for decades, until very recently when the air HSF setups became these bricks with massive server-like fans strapped on them.

Intel added an extra pipeline stage to Golden Cove because they still haven't gave up on their Netburst dream of 20 years ago. That extra pipeline stage would have gave them 2-4% extra performance per clock so Golden Cove might have been 21-23% faster per clock, not 19%. The extra pipeline stage also increases complexity and thus transistors and thus power use. This explains the less than expected perf/clock gain.

If you need nothing but the fastest performance, this may be the way to go, but at a sacrifice of everything else. The inefficient Golden Cove means you end up with inefficient Sapphire Rapids and inefficient mobile chips.

It's cute that anyone is even looking at the power consumption for all-core 5+ GHz overclocks. I bash on Intel for power usage issues all the time, but if you are going to compare Intel, let's compare performance based on a similar power envelope. That is, If you can't get Zen 3 to hit 5.3 GHz all core, don't look at Intel products that DO hit that point and claim they are inefficient. Take the max Zen 3 all core clocks and compare them to Intel equivalents, and see who gets more work done. Then we will have a starting point to see who is more efficient.

 

[geegee83]

Disregarding the uncore and the E core contribution to power, 233W to 330W is more than the voltage squared and frequency increase.

If you assume Golden Cove is only responsible for 180W out of that 233W, then you are talking 180W to 277W which is 24% above what V2F law would give you.

Don’t forget that leakage current has a cubic relationship to voltage.

 

[DrMrLordX]

Same story as with Rocket Lake, CPU-s are sold before official launch=still NDA in active.

Are people also getting boards to go with them?

Smaller cores are actually quite inefficient at full CPU throughput because they are fed the full voltage required by the big cores running at 5GHz.

A separate voltage rail for the small cores is necessary for full throughput being efficient, currently small cores are overvolted by something like 20% over what would be enough to get good stability at 3.7, that s roughly 40% more power than necessary.

That's a head-scratcher. How in the heck did Intel NOT put them on separate voltage domains?

Apparently they also confirmed that Meteor Lake uses a foundry node for some portion of it. I wonder if this does mean that the CPU tile is being dual sourced.

Probably necessary for reasons of volume. There won't be that much "Intel 4" to go around.

 

[IntelUser2000]

That's a head-scratcher. How in the heck did Intel NOT put them on separate voltage domains?

@Abwx explains it fairly well in post #13774.

So they'd have actually had to make up a desktop oriented chip, and they didn't. It's a scaled up mobile chip.

 

[semiman]

For about 10% IPC increase versus Zen3, Golden Cove looks to be very inefficient power wise. I don't know if it's the issue with the process node or uarch. itself, but perf./watt is noticeably worse. Especially if you take into consideration die size and how much intel invested in beefing up the core.

We already know how big Golden coves are by looking at Sapphire rapids dies. Since Intel 10 (7?) density is similar to that of TSMC7, a comparison is relatively easy.

Sapphire Rapids die uses 470sqmm of space with 15 cores(2 AVX512 units + IO in the same die) but Zen 3 uses 80sqmm of die space with 8 cores(10sqmm per core) without IO. Golden cove is way too big even if we take AVX512, IO, and higher clock margin (thus bigger unit cells) into account. Maybe more than 1.5x bigger? (In fact, Tiger lake is also bigger than Zen 3 but suffer from less IPC) more circuits for the same performance. more power is required.
Intel cove cores are suffering from per-core performance scaling. No wonder Intel plans 8+16 Raptor cove till the complete big core overhaul is done.

 

[Det0x]

There already is DDR5 memory with both a higher frequency and noticeably lower latency than what that poster used:

https://cdn.videocardz.com/1/2021/10/03-gskill-ddr5-6600-cl36-36-36-16gbx2-screenshot.png

6600 MT/s with CL36 is a 10.9 ns latency for the memory, who knows if the specific implementation would add more to that.

This is stock XMP

GALAXY publishes first benchmark results of its DDR5-4800 GAMER RGB memory - VideoCardz.com

GALAX Gamer DDR5-4800 CL36 tested in AIDA64 Galaxy, the company behind the DDR5 Gamer memory with LEGO-compatible parts, has now published the first test results of the new memory standard on social media. GALAX Gamer DDR5 RGB, Source: Galax Galaxy Gamer memory was first shown last week, as the...

videocardz.com

 

[JoeRambo]

XMP

Bandwidth of DDR4 4200 and latency of mobile phone. Achievement in handicapping stock performance of your new CPU core is now unlocked.
AMD is laughing at this point, compared to their amazing efforts solving latency with real problem of IMC being on separate IOD, this is just horrible engineering.

 

[Hans Gruber]

Remember when DDR4 came out and the performance of the high end DDR3 chips were better than DDR4? I guess that will not be the case with DDR5, it's supposed to have significant improvements. I am hoping Alder Lake does well. AMD is highly skilled at cutting prices and undercutting Intel. I am going to be quite honest here. AMD has basically dropped the ball in the last 6 months. This is intel we are talking about. Those greedy bastards don't like to lose. Now if Alder Lake CPU's are very good and take enough energy to power a small country. That would be a loss. The Alder Lake CPU's can run DDR4 or DDR5 which should produce some very interesting benchmarks to compare.

I am have been preparing for Alder Lake for the last couple of weeks. I dropped a significant chunk of change on a Rog Strix B450-F ($90) to replace my ancient B350. Now I am can get whatever Zen3 processor I want. I have no need for PCI-4 or gigabit 2.5 ports. I just need something to hold me over for a couple of years until DDR5 prices come down.

 

[DrMrLordX]

@Abwx explains it fairly well in post #13774.

So they'd have actually had to make up a desktop oriented chip, and they didn't. It's a scaled up mobile chip.

Intel would have been better-served by going with two rails, even if it cost them a little more per chip and added a little complexity. Even those non-OC power results are a bit ugly. If they could dial it back a little then it would be good for Alder Lake-S and great for Alder Lake-P.

 

[Abwx]

Intel would have been better-served by going with two rails, even if it cost them a little more per chip and added a little complexity. Even those non-OC power results are a bit ugly. If they could dial it back a little then it would be good for Alder Lake-S and great for Alder Lake-P.

If small cores optimal voltage result in 50W power then 20% overvoltage result in 25W more power, that s not enough delta to make a dual rail relevant given not only cost/complexity but also reliability, not counting complicated power management.

And as said in mobile P cores will clock close to the E cores frequencies, hence E cores overvoltage will be only 4% if P cores work at 4GHz.

 

[Asterox]

https://twitter.com/x/status/1451109571544555530

From 4.9-->5.2 Ghz= +100W
From 5.2-->5.3 Ghz=+70W

Voltage too high, Golden Cove scaling is off. At 4.0 Ghz (i5-12400) Golden Cove is probably a very efficient core but not at around 5 Ghz.

As expected, "in real world bench as Cinebench+i9 12900K(stock setings) will need 100W+ more for very similar R9 5950X score."

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[DrMrLordX]

that s not enough delta to make a dual rail relevant given not only cost/complexity but also reliability, not counting complicated power management.

How would the chip become less reliable? Is Intel really that incompetent?