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Discussion Intel current and future Lakes & Rapids thread

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JoeRambo said:
Great work, but i think same core count CPUs should be compared. 3300X is quad that has all resources of full chip to itself, while 8C of 5800X have twice as many cores sharing resources.
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Testing was done in this manner to keep L3 per core the same. Both are valid ways of testing at the end of the day though tbf.
 
I wonder how ADL-S will handle MT loads (by default) once the first 8 threads are distributed among the big cores. Back when doing napkin performance estimates my immediate expectation was that it would distribute threads on the small cores before using SMT on the big cores.

This approach would likely maximize hroughput, but does require some compensation mechanic to ensure latency sensitive workloads stay on the big cores even at the cost of prematurely using SMT capability. Granted I'm also ssuming the small core clusters will have significantly higher inter-core latencies, which is still a mere assumption at this point.

On one side I find all this very interesting from a theoretic point of view, on the other side I find that Apple's (rumored) approach with fewer small cores to be far easier to manage in terms of performance consistency. Then again it's nice to see so many different approaches clashing in the near future.
 
DrMrLordX said:
Which node does Intel currently use for their off-die PCH? 22nm?
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All I know off hand is that B360 were 14nm and the B365 "update" was really a 22nm change.

I'll find the source later, not sure if that was Anandtech coverage or what. It was sort of a weird deal, because B365 is not a super set of B360, features were lost and gained.
 
blckgrffn said:
*ahem*

Intel thread.

That is all 😉
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I avoided replying for this reason. 🤣
coercitiv said:
I wonder how ADL-S will handle MT loads (by default) once the first 8 threads are distributed among the big cores. Back when doing napkin performance estimates my immediate expectation was that it would distribute threads on the small cores before using SMT on the big cores.

This approach would likely maximize hroughput, but does require some compensation mechanic to ensure latency sensitive workloads stay on the big cores even at the cost of prematurely using SMT capability. Granted I'm also ssuming the small core clusters will have significantly higher inter-core latencies, which is still a mere assumption at this point.

On one side I find all this very interesting from a theoretic point of view, on the other side I find that Apple's (rumored) approach with fewer small cores to be far easier to manage in terms of performance consistency. Then again it's nice to see so many different approaches clashing in the near future.
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Microsoft needs to change the Windows scheduler to behave more like macOS: https://arstechnica.com/gadgets/202...-cpu-but-m1-macs-feel-even-faster-due-to-qos/
 
coercitiv said:
FYI
View attachment 45269
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Where is that from? Is that comparing Rocket Lake to 8+8 Alder Lake? If so then that would roughly translate to Alder Lake 8+8 being as fast in some situations as the 5950X, or as we've been speculating around here somewhere between 5900X and 5950X performance.

From the Ars article linked. Interesting strategy.

"What makes the Apple M1 feel so fast isn't the fact that four of its cores are slower than the others—it's the operating system's willingness to sacrifice maximum throughput in favor of lower task latency."
 
IntelUser2000 said:
That could always mean on mobile parts. I don't know how that's possible on desktop.
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That's why my original post was about the different requirements of the desktop platform, I was wondering how they would tackle the use of SMT on the big core vs. firing up a small core instead.

The point of my latter replies containing slides related to Alder Lake and Lakefield was to prove that Intel already has the software (and hardware) in place to prioritize foreground tasks (unless they've been lying about Lakefield all along). The common part of the hybrid problem that they share with Apple is already addressed.

Moving away from that though, in high performance systems, Apple doesn't face the same problems as Intel when it comes to hybrid chips. First, they lack SMT, so their priority list is quite simple. Second, if the rumors are true, in performance chips they prioritize big core count over small core with a ratio of 4:1, so ensuring consistent performance won't be much of an issue, if any at all.
 
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coercitiv said:
That's why my original post was about the different requirements of the desktop platform, I was wondering how they would tackle the use of SMT on the big core vs. firing up a small core instead.
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That's not hard to predict, isn't it? For thread allocation : Big core > small core > SMT.
 
Intel also has to be concerned about comparisons to AMD so while snappy response may be important to the end user, I would think tuning for benchmarks is also going to be high on the "to-do" list. I'm sure they're finding the optimum allocation of cores for Cinebench MT as I type this😉
 
About ADL scheduling:
Additionally, Intel and Microsoft are working close to optimize Alder Lake CPU performance for an upcoming build of its Windows operating system which will bring massive scheduling upgrades & will also be coming out around the same time as the launch of Alder Lake chips. The first unveiling is expected on the 24th of June.
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wccftech.com

Intel 10nm Alder Lake Desktop CPUs Launching During Halloween 2021, Will Feature Support On New LGA 1700 Socket Motherboards

Intel's 12th Generation Alder Lake K-series desktop CPUs based on the 10nm Enhanced SuperFin architecture are expected to launch in October.
wccftech.com wccftech.com

https://twitter.com/x/status/1400367814440013826
 
Zucker2k said:
Additionally, Intel and Microsoft are working close to optimize Alder Lake CPU performance for an upcoming build of its Windows operating system which will bring massive scheduling upgrades & will also be coming out around the same time as the launch of Alder Lake chips. The first unveiling is expected on the 24th of June.
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Hmm, seems like this is in conflict with Thala's earlier assertion that the scheduler isn't being changed for Alder Lake. Note: I believe you Zucker2k.
Thala said:
Not sure why you are speculating. The heterogenous Windows scheduler is already implemented and is used for every device which features heterogenous core configurations.
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Thala said:
Besides even if this would be the case, it would not change the scheduler at all...
You have to understand, that this feature (mapping certain threads to a subset of available cores) is supported since literally forever - and is not new feature with respect to the heterogenous scheduler discussed in this context.
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uzzi38 said:
This is BS.
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Is the idea of changing the scheduler BS (changing the scheduler for better performance of new chips is wrong), or is the content of the post BS (the scheduler change won't happen)? I wasn't sure which you were referring to.
 
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