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Discussion Intel current and future Lakes & Rapids thread

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Thala

Golden Member
Nov 12, 2014
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It is BS because:

The Windows scheduler added support for heterogenous scheduling which took into account the app intent for scheduling on big.LITTLE architectures.
By app intent, I mean Windows tries to provide a quality of service for apps by tracking threads which are running in the foreground (or starved of CPU) and ensuring those threads always run on the big core. Whereas the background tasks, services, and other ancillary threads in the system run on the little cores. (As an aside, you can also programmatically mark your thread as unimportant which will make it run on the LITTLE core.)
Work on Behalf: In Windows, a lot of work for the foreground is done by other services running in the background. E.g. In Outlook, when you search for a mail, the search is conducted by a background service (Indexer). If we simply, run all the services on the little core, then the experience and performance of the foreground app will be affected. To ensure, that these scenarios are not slow on big.LITTLE architectures, Windows actually tracks when an app calls into another process to do work on its behalf. When this happens, we donate the foreground priority to the service thread and force run the thread in the service on the big core.
Quote above coming form Microsoft and not from some dubious source. The scheduler is already working perfectly fine, which you can see when you happen to have a Windows big.LITTLE machine (perhaps excluding Lakefield)

I also posted a picture of the task manager, showing the system services on the little cores, while the big cores are power gated - except the one big core, which running the foreground app here
 
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Hulk

Diamond Member
Oct 9, 1999
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So the next version of Window will either have big scheduler changes or none at all for Big/Little.

More importantly Microsoft needs to make Windows easily customizable. Like being able to remove "3D Objects" or "Quick Launch" or a number of other apps forced on us removeable with a single right-click delete action. Stop adding garbage, it's just an OS that hosts the programs that do the real work.
 

dullard

Elite Member
May 21, 2001
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It is BS because:

Quote above coming form Microsoft and not from some dubious source. The scheduler is already working perfectly fine, which you can see when you happen to have a Windows big.LITTLE machine (perhaps excluding Lakefield)

I also posted a picture of the task manager, showing the system services on the little cores, while the big cores are power gated - except the one big core, which running the foreground app here
The key being that Alder Lake isn't big.LITTLE. Alder Lake is big.Medium (I refuse to use Intel's big.bigger terminology). Thus the need for changes to the scheduler. You are correct that Windows has had big.LITTLE for quite some time. But that isn't what Alder Lake uses or what Alder Lake is intended for.
 

Hulk

Diamond Member
Oct 9, 1999
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The key being that Alder Lake isn't big.LITTLE. Alder Lake is big.Medium (I refuse to use Intel's big.bigger terminology). Thus the need for changes to the scheduler. You are correct that Windows has had big.LITTLE for quite some time. But that isn't what Alder Lake uses or what Alder Lake is intended for.
Do we know if the scheduler is currently only optimized for Big/Little or if it's for heterogeneous CPU's in general? If it's the latter then ADL should be fine.
 

Hulk

Diamond Member
Oct 9, 1999
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how does big medium change anything, its only if you had big medium little would you do something different.

IE. list the exact use case where the scheduling method for big little would be different for big medium.
I was thinking the same thing but am not by any means an expert on this, which is why I posed the question. The only think I can think is that if part of the scheduler strategy is to assign the smaller cores to the OS most of the time, this could be overkill for medium cores.
But as I said I really don't know what the hell I'm talking about. But I find this topic very interesting.
 

Thala

Golden Member
Nov 12, 2014
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The key being that Alder Lake isn't big.LITTLE. Alder Lake is big.Medium (I refuse to use Intel's big.bigger terminology). Thus the need for changes to the scheduler. You are correct that Windows has had big.LITTLE for quite some time. But that isn't what Alder Lake uses or what Alder Lake is intended for.
This does not change anything. They key here is, that the heterogenous scheduler is aware of different performance points - if you call this big.LITTLE, big.bigger or big.Medium is irrelevant for the scheduler.
As itsmydamnation was pointing out above as well, the scheduling method/heuristic stays the same.
 

Magic Carpet

Diamond Member
Oct 2, 2011
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A couple of questions guys, why Rocket Lake S doesn’t support fivr since it’s based on post Icelake tech that does? And second, what is Intel’s next desktop processor (well minus the Tiger Lake limited edition bga part) with avx512? Thanks.
 

coercitiv

Diamond Member
Jan 24, 2014
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This does not change anything.
Sure it does, changing the name from small to medium brings a 10-15% performance uplift at the very least. You're new around here, aren't you? Let me give you the talking points:
  • First we have a discussion about how most people don't really require more than a 4c/8t CPU for their daily computing needs, since any more cores would not impact perceived performance by a significant margin. Multitasking is way overrated.
  • Then we have a discussion about how most people could benefit from a hybrid architecture and QoS aware scheduler that would surely impact perceived performance on the "resource starved" 4-core CPU that was more than good enough for multitasking just a month ago.
And this is how we get from not needing 6-8 classic cores on a modern desktop, but needing 6+ hybrid cores with additional scheduler optimizations on top to make everything work "faster". You see, this is why YOU don't work in Marketing, you common sense engineer! /s
 

Asterox

Senior member
May 15, 2012
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It is hard to find a words for this. Hm, lost in the woods of smoothly video playback. Completely useless, "in reality that PC also could be a AMD Ryzen PC".It is absurd for a company like Intel, to do such useless "imagine that it is Alder Lake PC and laptop".

 

Shivansps

Diamond Member
Sep 11, 2013
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Windows scheduler supports big.Little, they needed that for the Surface Pro X and i dont think big.MEDIUM changes anything, but ARM is going big.MEDIUM.Little with X1-A78-A55 and X2-A710-A510, so Windows will have to detect and support that more sooner than late. So if scheduler changes are needed they will come.

My only real question here is that if the scheduler knows what to do when there are little cores and big cores with HT. Or how well the thread affinity will work on x86 in a big.Little configuration when apps dont even consider that to be a thing. Because i now think that, for example, a game, should only be run on the big cores and no thread should be assigned to a little core. At first i trought that some small tasks could be assigned to small cores, but that may drag everything down really.
 
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Thala

Golden Member
Nov 12, 2014
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And this is how we get from not needing 6-8 classic cores on a modern desktop, but needing 6+ hybrid cores with additional scheduler optimizations on top to make everything work "faster". You see, this is why YOU don't work in Marketing, you common sense engineer! /s
And the irony is, that the desktop hybrid solution from Intel is not born from the fact, that Intel sees a particular advantage for desktops but it is here, because Intel was unable to reach their power and area targets with just large cores alone, because they are so highly inefficient - both from area and power perspective. So they make a virtue out of necessity.
 

Hulk

Diamond Member
Oct 9, 1999
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It is hard to find a words for this. Hm, lost in the woods of smoothly video playback. Completely useless, "in reality that PC also could be a AMD Ryzen PC".It is absurd for a company like Intel, to do such useless "imagine that it is Alder Lake PC and laptop".

Did you hear? They're "eggs-za-cuting."
 

ashFTW

Member
Sep 21, 2020
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That die shot is obviously incorrect, @ashFTW already confirmed multiple times that SPR is 80 cores based on physical evidence.
i revised it to 72 cores. I still believe that to be true, unless Intel only made one tile that has to work in both x2 and x4 configurations, in which case more I/O and mem controllers have to be put on each tile, reducing the number of cores that it can be accommodate.
 

uzzi38

Golden Member
Oct 16, 2019
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i revised it to 72 cores. I still believe that to be true, unless Intel only made one tile that has to work in both x2 and x4 configurations, in which case more I/O and mem controllers have to be put on each tile, reducing the number of cores that it can be accommodate.
...

I'm truly speechless.
 

jpiniero

Diamond Member
Oct 1, 2010
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i revised it to 72 cores. I still believe that to be true, unless Intel only made one tile that has to work in both x2 and x4 configurations, in which case more I/O and mem controllers have to be put on each tile, reducing the number of cores that it can be accommodate.
If you look at the die shot the bottom area doesn't look like an extra row of cores. I suppose it's possible that the die used is very old and the final version has 76 (72).

I think there will be a 2 die configuration for Xeon W/HEDT but that would be quad channel.
 

ashFTW

Member
Sep 21, 2020
27
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i revised it to 72 cores. I still believe that to be true, unless Intel only made one tile that has to work in both x2 and x4 configurations, in which case more I/O and mem controllers have to be put on each tile, reducing the number of cores that it can be accommodate.
That would be a pretty lazy thing to do, given Intel in the past has made several die sizes for each Xeon generation.

SPR supports uncore of 8 DDR5, and 80 PCIe 5.0, and up to 4 UPI. Let’s look at the options to achieve this in 2 and 4 tiles.

Tile A: all core
Tile B: half of uncore, rest core
Tile C: one fourth of uncore, rest core

to achieve medium and small configurations: two B tiles
to achieve larger configuration: 1) two A and 2 B tiles 2) four C tiles, or 3) four B tiles

if Intel only made the B tile, then the max cores with 4 tiles will be close to 60. If they made B and C, or A and B, they can go up to 72.

Lets wait and see.
 
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repoman27

Member
Dec 17, 2018
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If you look at the die shot the bottom area doesn't look like an extra row of cores. I suppose it's possible that the die used is very old and the final version has 76 (72).

I think there will be a 2 die configuration for Xeon W/HEDT but that would be quad channel.
So you think it is possible Intel taped out, produced a full set of masks, and manufactured a 15 core tile and then scrapped that and started all over again with a larger 19 core design? That is... highly unlikely.

That would be a pretty lazy thing to do, given Intel in the past has made several die sizes for each Xeon generation.

SPR supports uncore of 8 DDR5, and 80 PCIe 5.0, and up to 4 UPI. Let’s look at the options to achieve this in 2 and 4 tiles.

Tile A: all core
Tile B: half of uncore, rest core
Tile C: one fourth of uncore, rest core

to achieve medium and small configurations: two B tiles
to achieve larger configuration: 1) two A and 2 B tiles 2) four C tiles, or 3) four B tiles

if Intel only made the B tile, then the max cores with 4 tiles will be close to 60. If they made B and C, or A and B, they can go up to 72.

Lets wait and see.
It's not lazy at all. The whole point of tiled design is reuse. The design and mask costs for newer manufacturing nodes are prohibitive unless you can achieve sufficient volume. Monolithic SoCs can only scale to a certain point and then you're forced to tile. I don't think Intel is disaggregating at all here, they're just designing specifically for multi-chip modules using advanced packaging techniques. Every SPR tile has 15 cores plus one quarter of the uncore stuff. A 4-tile package will have a maximum of exactly 60 cores.

That being said, I find it interesting that Intel isn't using a single stepping for the tiles here. There are at least two that are sort of mirror images of each other—one with the memory controller on the left side and one with it on the right.

2d869490405feee3caa55d029503bf152273ed85.pngb9701b8a8010e666558072ed9d967130cf5ad56d.png36ef0f0bccbded79604ebed48d541cfbed6e730f.png0b8de0256493ac822fc6fd15d8eac3e094ae5ddb.pngE3H-e61VUAEP1eT.png

edit to add links to original image sources:
大IC微世界 Bilibili 2021-04-27
結城安穗-YuuKi_AnS Bilibili 2021-05-17
結城安穗-YuuKi_AnS Bilibili 2021-05-23
Raichu @OneRaichu Twitter 2021-06-05 (linked above)
 
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jpiniero

Diamond Member
Oct 1, 2010
9,339
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So you think it is possible Intel taped out, produced a full set of masks, and manufactured a 15 core tile and then scrapped that and started all over again with a larger 19 core design? That is... highly unlikely.
Given how long it must have been in development waiting for 10 nm, it doesn't seem that out of the question. They did the same thing with Skylake Server - they changed the layout from 25 cores to 28.
 

uzzi38

Golden Member
Oct 16, 2019
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That being said, I find it interesting that Intel isn't using a single stepping for the tiles here. There are at least two that are sort of mirror images of each other—one with the memory controller on the left side and one with it on the right.

View attachment 45361View attachment 45362View attachment 45363View attachment 45364View attachment 45365
There's also 2 EMIB bridges on the top and 3 on the left. Just another reason why they'd need a mirror die.
 

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