But we're looking at actual 10nm silicon here, not floorpan diagrams. Has anyone ever seen a 25-core SKL-SP die? This image came from a 2018 ISSCC conference presentation and merely illustrates the layout advantages of using tiled DDR4 controllers:Given how long it must have been in development waiting for 10 nm, it doesn't seem that out of the question. They did the same thing with Skylake Server - they changed the layout from 25 cores to 28.
Indeed. And that was visible from the initial photos which only showed the micro-bump fields.There's also 2 EMIB bridges on the top and 3 on the left. Just another reason why they'd need a mirror die.