Discussion Intel current and future Lakes & Rapids thread

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jpiniero

Lifer
Oct 1, 2010
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So you think it is possible Intel taped out, produced a full set of masks, and manufactured a 15 core tile and then scrapped that and started all over again with a larger 19 core design? That is... highly unlikely.

Given how long it must have been in development waiting for 10 nm, it doesn't seem that out of the question. They did the same thing with Skylake Server - they changed the layout from 25 cores to 28.
 

uzzi38

Platinum Member
Oct 16, 2019
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That being said, I find it interesting that Intel isn't using a single stepping for the tiles here. There are at least two that are sort of mirror images of each other—one with the memory controller on the left side and one with it on the right.

View attachment 45361View attachment 45362View attachment 45363View attachment 45364View attachment 45365
There's also 2 EMIB bridges on the top and 3 on the left. Just another reason why they'd need a mirror die.
 

repoman27

Senior member
Dec 17, 2018
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Given how long it must have been in development waiting for 10 nm, it doesn't seem that out of the question. They did the same thing with Skylake Server - they changed the layout from 25 cores to 28.
But we're looking at actual 10nm silicon here, not floorpan diagrams. Has anyone ever seen a 25-core SKL-SP die? This image came from a 2018 ISSCC conference presentation and merely illustrates the layout advantages of using tiled DDR4 controllers:

skylaake_server_layout_evoluation.png


There's also 2 EMIB bridges on the top and 3 on the left. Just another reason why they'd need a mirror die.
Indeed. And that was visible from the initial photos which only showed the micro-bump fields.
 
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Timmah!

Golden Member
Jul 24, 2010
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Cant they have both 15 and 19 core tile? Same way they had LCC, HCC and XCC dies for Skylake-X?
 

lobz

Platinum Member
Feb 10, 2017
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i revised it to 72 cores. I still believe that to be true, unless Intel only made one tile that has to work in both x2 and x4 configurations, in which case more I/O and mem controllers have to be put on each tile, reducing the number of cores that it can be accommodate.
Why would you make the hard decision of going with tiles with all their manufacturing advantages but many pitfalls too, only to go ahead and design multiple different tiles anyway?
 
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DrMrLordX

Lifer
Apr 27, 2000
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Dell is selling servers now with it. The one I checked does say it has a delivery date of August.

I'm shocked. They're finally ramping on that thing? I'd like to see Anandtech do a deep dive on Ice Lake-SP. I know they spent a little time with one earlier this year but all they did was some SPEC and NAMD if I recall correctly.
 
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dullard

Elite Member
May 21, 2001
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how does big medium change anything, its only if you had big medium little would you do something different.

IE. list the exact use case where the scheduling method for big little would be different for big medium.
I've given possible options several times in this thread already. Here is one of the times that I did so:

The main difference is that this is the first time that the cores do NOT have the same instruction set. Meaning Windows cannot just willy-nilly assign a thread to a core. That is a major and fundamental difference. They either need a method to prevent the wrong instruction going to the wrong core or a way to emulate the instructions that will crash the core that doesn't have the capability to run that instruction.

If you don't accept the tweet above from Moore's Law is Dead, then here is more information from Intel itself:
Gracemont also comes with increased vector performance, a nod to an obvious addition of some level of AVX support (likely AVX2). Meanwhile, the larger Golden Cove cores should support AVX-512. That split instruction set support could portend optimizations to the hardware-aware scheduler in the operating system, which we'll cover shortly.
...
There's already plenty of work underway in both Windows and various applications to support that technique via a hardware-guided OS scheduler. Still, the current format for Intel's Lakefield relies upon both cores supporting the same instruction set. Intel Chief Architect Raja Koduri mentioned that a new "next-generation" hardware-guided OS scheduler that's optimized for performance would debut with Alder Lake, but didn't provide further details. This next-gen OS scheduler could add in support for targeting cores with specific instruction sets to support a split implementation, but that remains to be seen.
Or you can go with rumors of the hardware-guided scheduling from Videocardz (see the left-central box):
 
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DrMrLordX

Lifer
Apr 27, 2000
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The main difference is that this is the first time that the cores do NOT have the same instruction set. Meaning Windows cannot just willy-nilly assign a thread to a core. That is a major and fundamental difference. They either need a method to prevent the wrong instruction going to the wrong core or a way to emulate the instructions that will crash the core that doesn't have the capability to run that instruction.

. . . or they'll just disable AVX-512 on Golden Cove and call it a day.
 

dullard

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May 21, 2001
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. . . or they'll just disable AVX-512 on Golden Cove and call it a day.
That is certainly an option. But, it is a pretty craptacular option for Intel. Build a whole new hybrid chip then disable the benefit of the hybrid chip. I can see why Intel might want to pay Microsoft to help develop a new scheduler instead.
 

Dayman1225

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Aug 14, 2017
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That is certainly an option. But, it is a pretty craptacular option for Intel. Build a whole new hybrid chip then disable the benefit of the hybrid chip. I can see why Intel might want to pay Microsoft to help develop a new scheduler instead.
I’m not sure how Intel disabling AVX-512 is disabling the benefit of Hybrid? The benefit of Hybrid is silicon area and power used. Oh and Intel will be going the route of disabling AVX-512 on the big cores to ensure ISA parity (this is basically confirmed) it makes things easy.
 

dullard

Elite Member
May 21, 2001
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I’m not sure how Intel disabling AVX-512 is disabling the benefit of Hybrid? The benefit of Hybrid is silicon area and power used. Oh and Intel will be going the route of disabling AVX-512 on the big cores to ensure ISA parity (this is basically confirmed) it makes things easy.
The concept of hybrid is to attempt to bring the best of both worlds together (mobile and desktop chip capabilities). Disabling key features is against that concept. Just go all mobile if you are going to disable the desktop features.

If the benefit of hybrid is silicon area, then you disable AVX-512, why bother to include it in the silicon? Do you have a source that confirms that AVX-512 will be disabled?

Intel does have a poor track record of opening up new paradigms (in this case, a 3rd chip type between mobile and desktop). See Optane for a great example, really powerful and really useful in some situations, but Intel basically killed it by implementing it poorly. But that doesn't mean that Intel won't try again.
 

Shivansps

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Sep 11, 2013
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There is just no way for the scheduler to know if the .exe uses AVX unless it reads the entire file (and libs, what is impossible).

So thats something that cant be fixed, Intel needs to come up with a way to handle that at hardware level.
 

DrMrLordX

Lifer
Apr 27, 2000
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The only advantage I can see to Alder Lake supporting AVX-512 is that it has some ML-accelerating extensions associated with it. Tiger Lake supports those currently.
 

dullard

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May 21, 2001
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There is just no way for the scheduler to know if the .exe uses AVX unless it reads the entire file (and libs, what is impossible).

So thats something that cant be fixed, Intel needs to come up with a way to handle that at hardware level.
That is why Intel keeps mentioning a new hardware-guided scheduler.
 

jpiniero

Lifer
Oct 1, 2010
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If the benefit of hybrid is silicon area, then you disable AVX-512, why bother to include it in the silicon? Do you have a source that confirms that AVX-512 will be disabled?

Embedded customers? You can turn off the small cores and get AVX-512 enabled.
 

coercitiv

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Jan 24, 2014
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That is why Intel keeps mentioning a new hardware-guided scheduler.
Do you have a source that confirms Hardware-Guided Scheduling has anything at all to do with enabling different instruction sets across a hybrid core configuration?
 

SAAA

Senior member
May 14, 2014
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All this AVX-512 debacle, is there some instruction difference between icelake and tremont on Lakefield someone could try? Or on the ARM side with big-little, say even outside windows? If those can do heterogeneous multi-processing already I see no issues, it's not like Alder will go back to cluster switching ( and it probably couldn't given the various big-small core counts) and disabling AVX512 makes no sense when Cannon, Ice, Tiger and Rocket Lake had it.
 

dullard

Elite Member
May 21, 2001
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Do you have a source that confirms Hardware-Guided Scheduling has anything at all to do with enabling different instruction sets across a hybrid core configuration?
Only the sources that Zucker2k and I linked above. But the assertion here is that the Windows scheduler will not be changing. It is up to the people making that assertion to prove it. Not the other way around (for me to disprove someone else's claims).