Depends on how much they can charge tbh if they can get $1000+ for that sku it's fine.
Uhh it's bLLC extra cache is costly in area what did you expect. In the end for bLLC gaming performance will decide it's fate cause people don't use their brains when buying SKU look at X3D.
110mm2 sounds pretty large, but if ARL-S's compute tile is ~115mm2, and whatever node shrink benefits they get are eaten up by increasing area for IPC on the P-cores, and enabling AVX-512 on the E-cores...
Well now that you think ARL is 117mm2 and if the core has 30-40% resourcing increase this size is reasonable you have AVX-512/APX taking area
I didn't even realise ARL 8+16 was already that big.
Pretty normal for 24 cores a tile.
Well it does, relative to all-Cove config.
20$ a core sounds reasonable
Uhh if it was not heterogenous and Intel didn't have Atom they would be over like way more area than this considering ratio of 2.25: for P:E in ARL for Core+L1
It's people not being able to measure image of slide lmao I can do better job than them considering package size is same as arrow.
He has split out two die sizes if you see his latest post and previous post
You only saw that now lmao look at the die size in that he is saying something else than before I am not believing anything at this point
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