You are saying it will be based on 10nm, to be exact it will be (most likely) based on 10ESF, I don't think the max clock speed is a problem. Intels big cores are too power hungry unless they are clocked really low, on 10nm at least. They cannot add the same amount of big cores as AMD. Also Willow Cove is quite a lot bigger than Zen3 and Golden Cove likely will be even bigger than Willow Cove, this is another issue with a limited 10nm capacity and subpar yields. There are a few reasons for Intel to go for the big+little route.
On the issue of size I have to say Intel 10SF process has definitely one good point: same density as 7nm from TSMC.
Looking at the picture I posted above the L2 is 0.5 MB vs 1.25 MB in 0.8 and 2 mm^2 square respectively, the density comes out equal for SRAM in actual products, at about the same running frequencies. With the caveat that Tigerlake 8 core might push above 5GHz turbo, without overclocking.
As for big little… if small cores are this small I seriously wonder why they don't plan to release parts entirely made of them, or like 4+16 small cores, 8+32 small and so on.
Even servers where frequencies are usually lower so not as big an issue… with rumors for Icelake server parts in the 370 to 640mm^2 range why not release a 128 or 256 core Gracemont? Those 256 cores could fit in the small dice range!
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