Canon's NZ3C w/ 200 wafers per hour is expected by fourth quarter 2018 to second quarter 2019.
NZ2C w/ Upgrade -> >80 wafers per hour and 0.1 defect density w/ 3.5-nm overlay (NAND and RAM)
NZ3C -> <200 wafers per hour and 0.01 defect density w/ sub-3.5 nm overlay. (Logic)
From 10nm ArF SAQP to JFIL NZ3C 1P is >45% savings over twice the savings of going EUV.
The 10nm JFIL process will be comparable to 5nm EUV processes. While, the 7nm JFIL process is aiming for 3nm EUV sub-22 metal pitch and sub-40 cpp/cgp pitch.
10nm Low Cost from Intel will be higher performance and more affordable than other foundry 7nm/5nm processes. (10GP(ArF)/10HPM(ArF)/10LC(JFIL))
7nm custom foundry will also be higher performance and more affordable than other foundry 3nm/2.5nm processes. (7xx(JFIL), +(JFIL), ++(JFIL)))
My elusive unnamed sources, HVM will be marked by JFIL w/ NZ3C. There is also a planned upgrade for the NZ3C included with an agreement. (Intel is also looking at Silicene mono-layer FinFETs. Which has been implemented with nanoimprint first.)