Discussion Intel current and future Lakes & Rapids thread

[Thunder 57]

If AMD lacks a feature, that feature sucks.
If AMD has a feature that Intel doesn't, it is the most vital feature known to man.

Rinse and repeat.

Uhh, I didn't read it that way. Multiple people including myself were just pointing out that having an iGPU on a mainstream 8 core part is useful, maybe even necessary based on market conditions.

 

[IntelUser2000]

This one?

Yes.

That was leaked way before we knew Cannonlake was only going to end up in couple of niche devices. It's especially interesting because they must have thought of expanding graphics even before then(because they had to plan in advance to get to that point). And considering time it takes for customization and for integration, Kabylake-G could have been conceived about that time.

I think it makes sense for even high end server chips like the one Purley uses. They spent that much resources and manpower on making graphics, why not use it? They advertise CAD software acceleration on their Xeon E3 chips, they have VCA for many display setups. Unless they were planning on canning graphics development entirely(basically, the mindset of we're not competitive so lets roll over and die?), ambitions will increase and therefore proliferation.

This then becomes the next step, and with Purley you'd have an option of a powerful GPU and powerful CPU. It's interesting what they would have really done with it.

 

[LTC8K6]

I mean the hardware decoder, using Microsoft's codecs.

But which generation? KL seems to be pretty good.

 

[Tup3x]

But which generation? KL seems to be pretty good.

Skylake (with Iris Graphics).

 

[Beemster]

https://www.semiwiki.com/forum/content/7496-imec-technology-forum-gary-patton-globalfoundries.html

It sounds like Agnello and the IBM folk did OK. I worked for Patton for a while in the 90s. He is pretty good also. Based on this, it looks like GF is on schedule to begin (as fast follower to TSMC) volume EPYC 2 7nm product by Nov 1.
An April 1 launch is possible. (no fooling)

Intel could be in for a world of trouble. (that's a new paragraph)

 

[Ajay]

Afshar getting pretty salty on Intel's 10nm.

Intel 10nm is not worth fixing. By the time they get it into HVM, it'll still be behind what the foundries are doing. They need to cancel this thing and throw everything at getting 7nm ready to go. 10nm is a non-viable piece of shit.

https://twitter.com/TMFChipFool/status/1002940084663054336

Now I really wonder how good Intel's IceLake can be

 

[mikk]

This is his personal opinion rant and nothing more. He also claimed i7-8086K is a fake multiple times, it isn't.

 

[jpiniero]

Even though it might take that long to fix 10 nm, Intel probably can't kill it because Granite Rapids likely relies on it for some tiles.

 

[Ajay]

Even though it might take that long to fix 10 nm, Intel probably can't kill it because Granite Rapids likely relies on it for some tiles.

Good point. I don't think Intel will cancel 10nm and I suspect that Afshar doesn't either - he just thinks they should. Anyway, Intel definitely needs a follow on to Cascade Lake so 10nm must live for the next server CPU to come out in a reasonable time frame.

 

[jpiniero]

Good point. I don't think Intel will cancel 10nm and I suspect that Afshar doesn't either - he just thinks they should. Anyway, Intel definitely needs a follow on to Cascade Lake so 10nm must live for the next server CPU to come out in a reasonable time frame.

Problem is, the higher the defect rate is, the worse the impact is on a bigger die. And Icelake Server is very likely completely monolithic. It might take until the end of next year to get to a decent yield rate for something tiny, let alone in the 400 mm2 range. Skipping Icelake Server for Sapphire Rapids would make sense assuming it allowed for smaller tiles but it's unclear where that is in the pipeline.

Edit: The Lenovo leak had the launch of Sapphire Rapids at the middle of 2020. Maybe that's what Intel will do, if things improve in time maybe ramp earlier for some higher 10 nm client %, otherwise ramp at the end of 2019 for SR's launch. Obvs pretty painful on server market share to wait that long but it's not like Intel has that great of other options.

 

[IntelUser2000]

Even though it might take that long to fix 10 nm, Intel probably can't kill it because Granite Rapids likely relies on it for some tiles.

You don't cancel Intel's 10nm for the same reason AMD couldn't have skipped a process to catch up - improvements don't come as a leap, but continuously, and you learn from what you did before.

 

[jpiniero]

You don't cancel Intel's 10nm for the same reason AMD couldn't have skipped a process to catch up - improvements don't come as a leap, but continuously, and you learn from what you did before.

True, but Intel's been at it for 2+ years now. How much left is there to learn, factoring in the fundamental problem with 10 nm shouldn't (heh) be an issue at 7 due to the switch to EUV although surely there will be new problems. I'm sure Intel has a drop-dead date in mind if yields don't improve but ironically if Intel has products in the pipeline that depend on 10 nm being there that complicates things.

 

[IntelUser2000]

It's easy as an outsider to tell them what they should be doing. But a team of world class engineers screwing up still knows better than anyone outside.

Ashraf is advocating they can development altogether and move to foundries. Of course with that line of thought, things as ludicrous as skipping a process makes sense. Unless they want to *really* kill development altogether they have to stick to it and fix it. What have they got to learn? Plenty! Because they are still having problems. Even if you are not you are still learning from it.

EUV is still likely at a state where they can use it only at critical layers. It's not a solution which will fix all problems and it brings its own set of issues.

 

[jpiniero]

EUV is still likely at a state where they can use it only at critical layers. It's not a solution which will fix all problems and it brings its own set of issues.

Samsung if I am not mistaken is using EUV fully at 7 nm, and based upon the comments they made about wafer output not too long ago is much further along than Intel's 10 at this point.

 

[NostaSeronx]

Canon's NZ3C w/ 200 wafers per hour is expected by fourth quarter 2018 to second quarter 2019.
NZ2C w/ Upgrade -> >80 wafers per hour and 0.1 defect density w/ 3.5-nm overlay (NAND and RAM)
NZ3C -> <200 wafers per hour and 0.01 defect density w/ sub-3.5 nm overlay. (Logic)

From 10nm ArF SAQP to JFIL NZ3C 1P is >45% savings over twice the savings of going EUV.

The 10nm JFIL process will be comparable to 5nm EUV processes. While, the 7nm JFIL process is aiming for 3nm EUV sub-22 metal pitch and sub-40 cpp/cgp pitch.

10nm Low Cost from Intel will be higher performance and more affordable than other foundry 7nm/5nm processes. (10GP(ArF)/10HPM(ArF)/10LC(JFIL))
7nm custom foundry will also be higher performance and more affordable than other foundry 3nm/2.5nm processes. (7xx(JFIL), +(JFIL), ++(JFIL)))

My elusive unnamed sources, HVM will be marked by JFIL w/ NZ3C. There is also a planned upgrade for the NZ3C included with an agreement. (Intel is also looking at Silicene mono-layer FinFETs. Which has been implemented with nanoimprint first.)

 

[Dayman1225]

You thought ICL-Y is a dualcore design? Looks like you are a little too pessimistic about ICL.


ICL-Y BGA1377 5.2W 4+2
https://www.ptt.cc/bbs/PC_Shopping/M.1503467362.A.A6A.html

Looks like Chrisdar was correct - Intel's own website leaked the BGA Pin count:

Source:
https://www.intel.co.uk/content/www/uk/en/search.html?toplevelcategory=none&query=ICL

It also confirmed many others:

Spoiler: Others

(ICL SP, ICL - D)

(CNL Y, CNL U)

(CLX SP, CLX AP)

(WHL U)

CNL-U : BGA1510

CNL-Y : BGA1392

WHL-U4(+)2 : BGA1528

CLX-SP : LGA3647

CLX-AP : BGA5903

ICL-Y: BGA 1377

ICL-U: BGA 1526

ICL-SP: LGA 4189

ICL-D: BGA 2579

 

[Dayman1225]

I also forgot to mention that Intel's Website also mention two other derivatives of the Icelake Core:

Icelake YN and Icelake UN, I have no idea what these are and what they do but compared to normal Icelake Y and U that was listed they have smaller BGA sockets.

(ICL UN, ICL YN)

ICL YN: BGA 1044

ICL UN: BGA 1344

Anyone have any ideas what this could be?

 

[mikk]

It could make sense for Intel to produce something smaller than initially planned because of the ongoing poor 10nm yields. Intel had troubles with the iGPU on Cannonlake and Icelake GT2 is even bigger, comes with 64 EUs fully enabled. Another option for ICL-YN is a dualcore version. The pin count is much smaller for YN. Other than that I have no idea what this could be.

 

[IntelUser2000]

It could make sense for Intel to produce something smaller than initially planned because of the ongoing poor 10nm yields. Intel had troubles with the iGPU on Cannonlake and Icelake GT2 is even bigger, comes with 64 EUs fully enabled. Another option for ICL-YN is a dualcore version. The pin count is much smaller for YN. Other than that I have no idea what this could be.

That makes no sense. They can do both using the same pin count.

 

[jpiniero]

I was thinking dual core too, but more GPU-less models is my other guess.

 

[IntelUser2000]

I was thinking dual core too, but more GPU-less models is my other guess.

Again, that makes no sense. You can do it using the same platform, which saves money. GPU-less also makes no sense on the low power platforms, especially at 5W.

On a side note:

I find it interesting that pin counts on both Cannonlake and Icelake are lower on the Y chips than on the U ones. It's the opposite for Broadwell, Skylake, and Kabylake.

ICL YN: BGA 1044

ICL UN: BGA 1344

Perhaps Icelake is more integrated and/or flexible and has some SoC functions on the main die. So they can forgo the PCH for saving costs and package size for extreme cost oriented applications. Which will reduce the pin count significantly.

 

[jpiniero]

Again, that makes no sense. You can do it using the same platform, which saves money. GPU-less also makes no sense on the low power platforms, especially at 5W.

It'd be okay for some embedded uses I would think. Does seem to be simply to lower packaging costs.

 

[IntelUser2000]

It'd be okay for some embedded uses I would think. Does seem to be simply to lower packaging costs.

It would make sense for a Xeon D part, or some industrial use, but most embedded use for client derived chips are used for display heavy applications like digital signage. At real low end you might not need display out either, but that's not what Icelake is. Quark is more suitable.

In any case, I don't think YN and UN will be worth caring for enthusiasts. We may never encounter them directly.

I find it interesting that pin counts on both Cannonlake and Icelake are lower on the Y chips than on the U ones. It's the opposite for Broadwell, Skylake, and Kabylake.

I hope this means the lower pin count and smaller package size will enable Intel to sell the -Y chips at noticeably lower prices than the -U chips. Rather than the pretend-Core they are today. Y chips at their current pricing are crap. Just bad.

 

[jpiniero]

https://pc.watch.impress.co.jp/docs/column/ubiq/1126720.html

Rumor suggesting 14nm Comet Lake U coming in 2019. Includes Icelake's PCH which adds Thunderbolt.

In any case, I don't think YN and UN will be worth caring for enthusiasts. We may never encounter them directly.

At this rate, Icelake Client looks like it is going to end up cancelled or at best get the Cannonlake treatment.

 

[JoeRambo]

So things got out of hand so bad, that chipset node cought with up "leading edge" that is used for CPUs? Must be pretty hard blow for what was premier manufacturer of silicon.